公开(公告)号：US09059046B2

公开(公告)日：2015-06-16

申请号：US13612590

申请日：2012-09-12

申请人： Shin Il Choi ,  Seung-Ha Choi ,  Bong-Kyun Kim ,  Sang Gab Kim ,  Sho Yeon Kim ,  Hyun Kim ,  Hong Sick Park ,  Su Bin Bae

发明人： Shin Il Choi ,  Seung-Ha Choi ,  Bong-Kyun Kim ,  Sang Gab Kim ,  Sho Yeon Kim ,  Hyun Kim ,  Hong Sick Park ,  Su Bin Bae

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/12

CPC分类号： H01L27/1225

摘要： A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于所述基板上并包括栅电极的栅极线; 位于栅极线上的栅极绝缘层; 位于所述基板上的氧化物半导体层; 位于所述氧化物半导体层上的源电极和漏极; 位于所述源电极和所述漏极上并且包括第一接触孔的第一绝缘层; 位于所述第一绝缘层上且与所述栅极线相交的数据线; 以及在所述第一绝缘层上方的像素电极。 源电极和漏极各自包含金属氧化物。 数据线通过第一接触孔与源电极电连接。

公开(公告)号：US20120133873A1

公开(公告)日：2012-05-31

申请号：US13193488

申请日：2011-07-28

申请人： Ji-Young PARK ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

发明人： Ji-Young PARK ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

IPC分类号： G02F1/1333 ,  H01L33/16

CPC分类号： H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  H01L29/41733

摘要： A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.

摘要翻译： 制造液晶显示器的方法包括：在第一基板上形成包括栅电极的栅极线; 在栅极线上形成栅极绝缘层; 在栅极绝缘层的整个表面上依次形成半导体层，非晶硅层和数据金属层; 对准半导体层和数据金属层的边缘; 在栅绝缘层和数据金属层上形成透明导电层; 通过图案化透明导电层形成第一像素电极和第二像素电极; 以及使用所述第一像素电极和所述第二像素电极作为掩模，通过蚀刻所述数据金属层和所述非晶硅层来形成包括源电极，漏电极和欧姆接触层的数据线，并且使所述半导体在 源电极和漏电极。

公开(公告)号：US08755019B2

公开(公告)日：2014-06-17

申请号：US13193488

申请日：2011-07-28

申请人： Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

发明人： Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

IPC分类号： G02F1/1339 ,  G02F1/13

CPC分类号： H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  H01L29/41733

摘要： A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.

摘要翻译： 制造液晶显示器的方法包括：在第一基板上形成包括栅电极的栅极线; 在栅极线上形成栅极绝缘层; 在栅极绝缘层的整个表面上依次形成半导体层，非晶硅层和数据金属层; 对准半导体层和数据金属层的边缘; 在栅绝缘层和数据金属层上形成透明导电层; 通过图案化透明导电层形成第一像素电极和第二像素电极; 以及使用所述第一像素电极和所述第二像素电极作为掩模，通过蚀刻所述数据金属层和所述非晶硅层来形成包括源电极，漏电极和欧姆接触层的数据线，并且使所述半导体在 源电极和漏电极。

公开(公告)号：US08383437B2

公开(公告)日：2013-02-26

申请号：US13223958

申请日：2011-09-01

申请人： Ji-Young Park ,  Shin-Il Choi ,  Jong-Hyun Choung ,  Sang Gab Kim ,  Seon-Il Kim ,  Sang-Tae Kim ,  Joon-Woo Lee ,  Young-Chul Park ,  Young-Jun Jin ,  Kyong-Min Kang ,  Suck-Jun Lee ,  O-Byoung Kwon ,  In-Ho Yu ,  Sang-Hoon Jang ,  Min-Ki Lim ,  Yu-Jin Lee

发明人： Ji-Young Park ,  Shin-Il Choi ,  Jong-Hyun Choung ,  Sang Gab Kim ,  Seon-Il Kim ,  Sang-Tae Kim ,  Joon-Woo Lee ,  Young-Chul Park ,  Young-Jun Jin ,  Kyong-Min Kang ,  Suck-Jun Lee ,  O-Byoung Kwon ,  In-Ho Yu ,  Sang-Hoon Jang ,  Min-Ki Lim ,  Yu-Jin Lee

IPC分类号： H01L21/00

CPC分类号： C09K13/08 ,  C23F1/18 ,  C23F1/26 ,  C23F1/44 ,  H01L21/32134 ,  H01L27/1259 ,  H01L29/41733

摘要： An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.

摘要翻译： 根据本发明的示例性实施方案的蚀刻剂包括约0.5重量％至约20重量％的过硫酸盐，约0.01重量％至约2重量％的氟化合物，约1重量％至约10重量％的无机酸， 约0.5重量％至约5重量％的环胺化合物，约0.1重量％至约5重量％的氯化合物，约0.05重量％至约3重量％的铜盐，约0.1重量％至约10重量％ ％的有机酸或有机酸盐，和水。

公开(公告)号：US08518731B2

公开(公告)日：2013-08-27

申请号：US13310005

申请日：2011-12-02

申请人： Jeong Min Park ,  Dong-Won Woo ,  Je Hyeong Park ,  Sang Gab Kim ,  Jung-Soo Lee ,  Ji-Hyun Kim

发明人： Jeong Min Park ,  Dong-Won Woo ,  Je Hyeong Park ,  Sang Gab Kim ,  Jung-Soo Lee ,  Ji-Hyun Kim

IPC分类号： H01L21/00

CPC分类号： H01L29/786 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/78645

摘要： A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

摘要翻译： 薄膜晶体管阵列板的制造方法包括：使用非过氧化物的蚀刻剂，在基板上同时形成栅极导体和第一电极; 在所述栅极导体和所述第一电极上形成栅极绝缘层; 在栅极绝缘层上形成半导体，源电极和漏电极; 在半导体，源电极和漏电极上形成钝化层; 以及在所述钝化层上形成第二电极层。

公开(公告)号：US20120273787A1

公开(公告)日：2012-11-01

申请号：US13244086

申请日：2011-09-23

申请人： Hwa Yeul OH ,  O Sung Seo ,  Je Hyeong Park ,  Shin II Choi ,  Dong-Won Woo ,  Ji-Young Park ,  Jean Ho Song ,  Sang Gab Kim

发明人： Hwa Yeul OH ,  O Sung Seo ,  Je Hyeong Park ,  Shin II Choi ,  Dong-Won Woo ,  Ji-Young Park ,  Jean Ho Song ,  Sang Gab Kim

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L27/1259 ,  G02F1/136286

摘要： In a thin film transistor array panel according to an exemplary embodiment of the present invention, a plasma process using a mixed gas including hydrogen gas and nitrogen gas with a ratio of a predetermined value is undertaken before depositing a passivation layer. In this manner, performance deterioration of the thin film transistor may be prevented and simultaneously, haze in a transparent electrode may be prevented. Alternatively, a first passivation layer is depsoited, then removed. A passivation layer is again re-deposited, such that little or no haze is present in the resulting passivation layer.

摘要翻译： 在根据本发明的示例性实施例的薄膜晶体管阵列面板中，在沉积钝化层之前进行使用包括氢气和含有预定值的氮气的混合气体的等离子体处理。 以这种方式，可以防止薄膜晶体管的性能恶化，并且同时可以防止透明电极中的雾度。 或者，第一钝化层被剥离，然后除去。 再次沉积钝化层，使得在所得钝化层中存在很少或没有雾度。

公开(公告)号：US09133550B2

公开(公告)日：2015-09-15

申请号：US13433013

申请日：2012-03-28

申请人： In-Bae Kim ,  Jong-Hyun Choung ,  Ji-Young Park ,  Seon-Il Kim ,  Jae-Woo Jeong ,  Sang Gab Kim ,  Sang-Woo Kim ,  Ki-Beom Lee ,  Dae-Woo Lee ,  Sam-Young Cho

发明人： In-Bae Kim ,  Jong-Hyun Choung ,  Ji-Young Park ,  Seon-Il Kim ,  Jae-Woo Jeong ,  Sang Gab Kim ,  Sang-Woo Kim ,  Ki-Beom Lee ,  Dae-Woo Lee ,  Sam-Young Cho

IPC分类号： C09K13/00 ,  C23F1/18 ,  C23F1/26 ,  H01L21/3213 ,  C09K13/08 ,  H01L27/12

CPC分类号： C23F1/18 ,  C09K13/08 ,  C23F1/26 ,  H01L21/32134 ,  H01L27/124

摘要： An etching composition, a method of forming a metal pattern using the etching composition, and a method of manufacturing a display substrate are disclosed. The etching composition includes about 0.1% by weight to about 25% by weight of ammonium persulfate, about 0.1% by weight to about 25% by weight of an organic acid, about 0.01% by weight to about 5% by weight of a chelating agent, about 0.01% by weight to about 5% by weight of a fluoride compound, about 0.01% by weight to about 5% by weight of a chloride compound, about 0.01% by weight to about 2% by weight of an azole-based compound and a remainder of water. Thus, a copper layer may be stably etched to improve a reliability of manufacturing the metal pattern and the display substrate.

摘要翻译： 公开了一种蚀刻组合物，使用该蚀刻组合物形成金属图案的方法以及一种制造显示衬底的方法。 蚀刻组合物包含约0.1重量％至约25重量％的过硫酸铵，约0.1重量％至约25重量％的有机酸，约0.01重量％至约5重量％的螯合剂 ，约0.01重量％至约5重量％的氟化物，约0.01重量％至约5重量％的氯化物化合物，约0.01重量％至约2重量％的唑类化合物 和余下的水。 因此，可以稳定地蚀刻铜层以提高制造金属图案和显示基板的可靠性。

公开(公告)号：US20130087800A1

公开(公告)日：2013-04-11

申请号：US13424278

申请日：2012-03-19

申请人： Pil Soon HONG ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

发明人： Pil Soon HONG ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

IPC分类号： H01L27/15 ,  H01L33/08

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

摘要翻译： 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

公开(公告)号：US07361606B2

公开(公告)日：2008-04-22

申请号：US11564308

申请日：2006-11-29

申请人： Sang Gab Kim ,  Shi Yul Kim ,  Min Seok Oh ,  Hong Kee Chin

发明人： Sang Gab Kim ,  Shi Yul Kim ,  Min Seok Oh ,  Hong Kee Chin

IPC分类号： H01L21/302

CPC分类号： C23F4/00 ,  C23F1/02 ,  C23F1/12 ,  H01L21/32136

摘要： A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

摘要翻译： 提供一种形成金属线的方法。 在基底基板上形成保护第一金属层的第一金属层和第二金属层。 第一金属层包括铝或铝合金。 在第二金属层上形成具有直线形状的光致抗蚀剂图案。 使用蚀刻气体和光致抗蚀剂图案作为蚀刻掩模对第一和第二金属层进行干蚀刻。 从基底基板去除刻蚀材料，以防止干蚀刻的第一金属层的腐蚀。 因此，可以通过干蚀刻工艺形成没有腐蚀的源极金属图案，从而降低了制造成本。

公开(公告)号：US08653530B2

公开(公告)日：2014-02-18

申请号：US13424278

申请日：2012-03-19

申请人： Pil Soon Hong ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

发明人： Pil Soon Hong ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

IPC分类号： H01L29/00

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

摘要翻译： 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。