公开(公告)号：US07848143B2

公开(公告)日：2010-12-07

申请号：US12687915

申请日：2010-01-15

申请人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

发明人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

IPC分类号： G11C16/00

CPC分类号： G11C16/3418

摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

摘要翻译： 存储器控制器控制包括非易失性存储单元的半导体存储器件。 控制器包括发生电路和选择电路。 生成电路基于第二数据生成第一数据。 选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。 选择电路选择第一数据之一。 所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。 选择电路将与所选择的第一数据相关的和保持为新的累积值。

公开(公告)号：US20100122147A1

公开(公告)日：2010-05-13

申请号：US12687915

申请日：2010-01-15

申请人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

发明人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/3418

摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

摘要翻译： 存储器控制器控制包括非易失性存储单元的半导体存储器件。 控制器包括发生电路和选择电路。 生成电路基于第二数据生成第一数据。 选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。 选择电路选择第一数据之一。 所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。 选择电路将与所选择的第一数据相关的和保持为新的累积值。

公开(公告)号：US20080205145A1

公开(公告)日：2008-08-28

申请号：US12039254

申请日：2008-02-28

申请人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

发明人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

摘要翻译： 存储器控制器控制包括非易失性存储单元的半导体存储器件。 控制器包括发生电路和选择电路。 生成电路基于第二数据生成第一数据。 选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。 选择电路选择第一数据之一。 所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。 选择电路将与所选择的第一数据相关的和保持为新的累积值。

公开(公告)号：US07796429B2

公开(公告)日：2010-09-14

申请号：US12039254

申请日：2008-02-28

申请人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

发明人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

IPC分类号： G11C16/06

CPC分类号： G11C16/3418

摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

公开(公告)号：US09128864B2

公开(公告)日：2015-09-08

申请号：US13724337

申请日：2012-12-21

申请人： Osamu Torii ,  Shinichi Kanno

发明人： Osamu Torii ,  Shinichi Kanno

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/1008 ,  G06F11/1044

摘要： According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.

摘要翻译： 根据一个实施例，存储器控制器包括编码单元，其为每个用户数据生成第一奇偶校验，并且为两个或更多个用户数据生成第二奇偶校验，以及相应的第一奇偶校验，存储器接口单元， 读出来自非易失性存储器的用户数据和奇偶校验，以及使用用户数据和奇偶校验执行纠错解码处理的解码单元。 使用第一奇偶校验和第二奇偶校验两者的纠错解码处理至少具有用于第一用户数据的校正能力的A（第一奇偶校正能力）+ B（第二奇偶校验的校正能力）比特及其 第一和第二奇偶校验以及第二用户数据及其第一和第二奇偶校验。

公开(公告)号：US08812774B2

公开(公告)日：2014-08-19

申请号：US13217461

申请日：2011-08-25

申请人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

发明人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/1068

摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.

摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

公开(公告)号：US08640013B2

公开(公告)日：2014-01-28

申请号：US13601707

申请日：2012-08-31

申请人： Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

发明人： Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

IPC分类号： H03M13/15

CPC分类号： G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/159 ,  H03M13/3715 ,  H03M13/3746

摘要： According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

摘要翻译： 根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量 的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

公开(公告)号：US08612824B2

公开(公告)日：2013-12-17

申请号：US13038804

申请日：2011-03-02

申请人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

发明人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G11C16/3418 ,  G11C16/00 ,  G11C29/028

摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.

摘要翻译： 半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。

公开(公告)号：US20130305120A1

公开(公告)日：2013-11-14

申请号：US13724337

申请日：2012-12-21

申请人： Osamu TORII ,  Shinichi Kanno

发明人： Osamu TORII ,  Shinichi Kanno

IPC分类号： G06F11/10

CPC分类号： G06F11/1008 ,  G06F11/1044

摘要： According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.

摘要翻译： 根据一个实施例，存储器控制器包括编码单元，其为每个用户数据生成第一奇偶校验，并且为两个或更多个用户数据生成第二奇偶校验，以及相应的第一奇偶校验，存储器接口单元， 读出来自非易失性存储器的用户数据和奇偶校验，以及使用用户数据和奇偶校验执行纠错解码处理的解码单元。 使用第一奇偶校验和第二奇偶校验两者的纠错解码处理至少具有用于第一用户数据的校正能力的A（第一奇偶校正能力）+ B（第二奇偶校验的校正能力）比特及其 第一和第二奇偶校验以及第二用户数据及其第一和第二奇偶校验。

公开(公告)号：US20130254637A1

公开(公告)日：2013-09-26

申请号：US13600929

申请日：2012-08-31

申请人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

发明人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： H03M13/05

CPC分类号： H03M13/05 ,  H03M13/6516

摘要： According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

摘要翻译： 根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。