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    Apparatus for concurrently testing a plurality of semiconductor memories in parallel
    1.
    发明授权
    Apparatus for concurrently testing a plurality of semiconductor memories in parallel 失效
    用于并行测试多个半导体存储器的装置

    公开(公告)号：US5646948A

    公开(公告)日：1997-07-08

    申请号：US297924

    申请日：1994-08-31

    申请人： Shinichi Kobayashi ,  Toshimi Ohsawa ,  Tadashi Okazaki ,  Kazumi Kita ,  Junichi Kanai ,  Tadahiko Baba

    发明人： Shinichi Kobayashi ,  Toshimi Ohsawa ,  Tadashi Okazaki ,  Kazumi Kita ,  Junichi Kanai ,  Tadahiko Baba

    IPC分类号： G01R31/3193 ,  G11C29/56 ,  G01R31/28 ,  G06F7/38 ,  G06F11/00 ,  G11C7/00

    CPC分类号： G01R31/31935 ,  G11C29/56

    摘要： A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate. When they match, a compared result that represents pass is output. When they mismatch, a compared result that represents fail is output. A match signal WC detected by the XOR gate is held in a register. The register outputs an inhibition signal to an inhibition gate of the test memory. Thus, a write enable signal WE is inhibited from being supplied to the test memory. In addition, the inhibition signal is supplied to a compared result inhibition gate. The compared result inhibition gate causes the compared result to be passed and prevents the test memory from being excessively written.

    摘要翻译： 测试数据模式，地址模式和控制信号从模式发生器提供给测试存储器。 从测试存储器读取的数据通过XOR门与预期数据进行比较。 当它们匹配时，输出表示通过的比较结果。 当它们不匹配时，输出表示失败的比较结果。 由异或门检测到的匹配信号WC被保存在寄存器中。 寄存器输出禁止信号到测试存储器的禁止门。 因此，禁止写使能信号WE被提供给测试存储器。 此外，禁止信号被提供给比较结果禁止门。 比较结果禁止门导致比较结果通过，并防止测试存储器被过度写入。

    Semiconductor memory testing device
    4.
    发明授权
    Semiconductor memory testing device 有权
    半导体存储器测试装置

    公开(公告)号：US07028236B2

    公开(公告)日：2006-04-11

    申请号：US09958860

    申请日：2000-12-06

    申请人： Tadashi Okazaki

    发明人： Tadashi Okazaki

    IPC分类号： G11C29/00

    CPC分类号： G11C29/56

    摘要： This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular memory block after a failure is detected in the block. The test system which tests writing and erasing as a unit of block in the memory under test. The test system includes a register provided for each memory under test for holding a first failure generated in a particular block at a first control signal from a pattern generator, establishes a pass result for the particular block for test cycles after the first failure, thereby treating any failure result for the particular block as the pass result thereafter; and resets the register at a cycle specified by a second control signal from the pattern generator to release the pass result.

    摘要翻译： 本发明提供一种半导体存储器测试系统，其中在块中检测到故障之后，测试系统将不对特定存储器块进行逻辑比较。 在被测内存中测试写入和擦除作为单元的测试系统。 测试系统包括为每个待测存储器提供的寄存器，用于保存来自模式发生器的第一控制信号在特定块中产生的第一故障，为第一故障之后的测试周期建立特定块的通过结果，从而处理 特定块的任何故障结果作为之后的通过结果; 并以来自模式发生器的第二控制信号指定的周期复位寄存器以释放通过结果。

    Address generating device for memory tester
    5.
    发明授权
    Address generating device for memory tester 失效
    地址生成装置用于记忆测试仪

    公开(公告)号：US6019501A

    公开(公告)日：2000-02-01

    申请号：US860017

    申请日：1992-03-30

    申请人： Tadashi Okazaki

    发明人： Tadashi Okazaki

    IPC分类号： G06F11/22 ,  G01R31/3181 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/56

    CPC分类号： G11C29/56 ,  G01R31/31813

    摘要： In an address generating device wherein addresses are generated by an address computation part in response to data and control signals read out of an instruction memory and are provided to a memory under test, a command control bit for storing a command control signal is provided in the instruction memory and a command register is provided for storing a command read out of a data area of the instruction memory. The output from the address computation part and the output from the command register are input into a first multiplexer, which selects either one of the two inputs in response to a command control signal read out of the command control bit. The output from the first multiplexer is applied to a descrambler, wherein it is translated to a physical address. A second multiplexer is provided for selecting either one of the outputs from the descrambler and the first multiplexer in such an instance. The second multiplexer is controlled by a descramble inhibit signal read out of a descramble inhibit bit in the instruction memory.

    摘要翻译： 在地址产生装置中，响应于从指令存储器读出的数据和控制信号，由地址计算部分产生地址，并将其提供给被测存储器，在该存储器中提供用于存储命令控制信号的命令控制位 提供指令存储器和命令寄存器，用于存储从指令存储器的数据区读出的命令。 来自地址计算部分的输出和命令寄存器的输出被输入到第一多路复用器中，该第一多路复用器根据从指令控制位读出的命令控制信号选择两个输入中的任一个。 来自第一多路复用器的输出被应用于解扰器，其中它被转换成物理地址。 在这种情况下，提供第二多路复用器用于选择来自解扰器和第一多路复用器的输出之一。 第二多路复用器由从指令存储器中的解扰禁止位读出的解扰禁止信号来控制。