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    Central processing unit including inhibited branch area
    1.
    发明授权
    Central processing unit including inhibited branch area 失效
    中央处理单元包括禁止分支区域

    公开(公告)号：US5630158A

    公开(公告)日：1997-05-13

    申请号：US361936

    申请日：1994-12-22

    申请人： Kazuhiko Hara ,  Shinichi Yamaura ,  Keiichi Yoshioka ,  Takao Katayama

    发明人： Kazuhiko Hara ,  Shinichi Yamaura ,  Keiichi Yoshioka ,  Takao Katayama

    IPC分类号： G06F9/26 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F9/00

    CPC分类号： G06F9/342 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3861

    摘要： A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.

    摘要翻译： 中央处理单元包括存储指令代码的指令寄存器，控制指令执行步骤的定时的定时控制单元，执行对数据的操作和暂时存储数据的执行单元，执行单元具有程序计数器和数据总线 应执行从指令寄存器读取的解码器解码指令代码和控制指令寄存器，定时控制单元和执行单元，以及接收指示进行下一条指令的指示信号的下一个使能单元，并且控制该指示的输出 基于第一和第二信号向指令寄存器和定时控制单元发送信号。 第一个信号从解码器提供，并指示数据总线上的数据输入到程序计数器。 第二信号从执行单元提供并指示程序计数器的计数器值是奇数还是偶数。

    Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core
    2.
    发明授权
    Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core 失效
    用于仿真CPU核心的仿真系统，具有用于仿真的CPU核心和具有CPU核心的ASIC

    公开(公告)号：US5594890A

    公开(公告)日：1997-01-14

    申请号：US200705

    申请日：1994-02-23

    申请人： Shinichi Yamaura ,  Keiichi Yoshioka ,  Kazuhiko Hara ,  Takao Katayama

    发明人： Shinichi Yamaura ,  Keiichi Yoshioka ,  Kazuhiko Hara ,  Takao Katayama

    IPC分类号： G06F11/22 ,  G06F11/36 ,  G06F17/00

    CPC分类号： G06F11/3652

    摘要： An IC is provided with a CPU core selected from a plurality of CPU cores, each of which has a specific function. Each CPU core has a system-bus terminal and a common emulator connecting-exclusive terminal. The IC is also provided with a predetermined function device connected to a system bus of the selected CPU core. An emulation bus connects an emulator to the selected CPU core via the common emulator connecting-exclusive terminal. An emulator performs emulation on the selected CPU core which is connected via the emulation bus when the selected CPU core is in a monitor mode. The number of terminal elements and the function associated with each terminal element of the common emulator connecting-exclusive terminal are identical among the common emulator connecting-exclusive terminals.

    摘要翻译： IC具有从多个CPU核心中选择的CPU核心，每个CPU核心具有特定功能。 每个CPU内核都有一个系统总线端子和一个通用的仿真器连接专用端子。 IC还具有连接到所选CPU核心的系统总线的预定功能装置。 仿真总线通过通用仿真器连接专用端子将仿真器连接到选定的CPU内核。 仿真器对选定的CPU内核进行仿真，当所选择的CPU内核处于监视模式时，通过仿真总线连接。 公共仿真器连接专用端子的终端元件数量和与每个终端元件相关联的功能在通用仿真器连接专用端子中是相同的。

    Microprocessor having function of prefetching instruction
    4.
    发明授权
    Microprocessor having function of prefetching instruction 失效
    具有预取指令功能的微处理器

    公开(公告)号：US5938758A

    公开(公告)日：1999-08-17

    申请号：US933579

    申请日：1997-09-19

    申请人： Takao Katayama ,  Shinichi Yamaura ,  Keiichi Yoshioka ,  Kazuhiko Hara

    发明人： Takao Katayama ,  Shinichi Yamaura ,  Keiichi Yoshioka ,  Kazuhiko Hara

    IPC分类号： G06F9/38 ,  G06F9/32 ,  G06F9/46 ,  G06F9/48 ,  G06F13/32 ,  G06F13/00

    CPC分类号： G06F9/32 ,  G06F9/3802

    摘要： A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.

    摘要翻译： 具有指令预取功能的微处理器包括存储电路，其中存储经由外部接口向外部提供给微处理器的指令，第一锁存电路，响应于外部提供给中断信号而锁存存储电路的写入地址值 微处理器和内部中断信号输出电路，其将指示存储在存储电路中的指令的存储电路的读取地址值与从第一锁存电路提供的写入地址值进行比较，并且仅在读取时产生内部中断信号 地址值和写入地址值彼此一致。 微处理器响应于内部中断信号处理中断过程。

    Register group circuit for data processing system
    5.
    发明授权
    Register group circuit for data processing system 失效
    数据处理系统寄存器组电路

    公开(公告)号：US5606709A

    公开(公告)日：1997-02-25

    申请号：US344365

    申请日：1994-11-23

    申请人： Keiichi Yoshioka ,  Shinichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama

    发明人： Keiichi Yoshioka ,  Shinichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama

    IPC分类号： G06F7/00 ,  G06F13/40 ,  G06F13/20

    CPC分类号： G06F13/4027

    摘要： A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal. The output register group includes a second part for driving the inner bus according to a state of the second bus.

    摘要翻译： 提供在数据处理系统中的通用寄存器组电路包括连接到第一总线和第二总线的多个寄存器组，经由第一总线根据第一控制信号被写入多个寄存器组的数据，并且 根据第二控制信号经由第二总线从其读取。 输出寄存器组经由第一和第二总线连接到多个寄存器组。 根据第三控制信号将从多个寄存器组读取的数据写入输出寄存器组，并且根据第四控制信号将从输出寄存器组读取的数据发送到数据处理系统的内部总线。 多个寄存器组中的每一个包括多个单元寄存器，其中每个寄存器包括用于根据锁存在其中的数据和第二控制信号将第二总线设置为高阻抗状态或参考电平的第一部分。 输出寄存器组包括用于根据第二总线的状态驱动内部总线的第二部分。

    Parallel processor and image processing apparatus
    6.
    发明申请
    Parallel processor and image processing apparatus 审中-公开
    并行处理器和图像处理装置

    公开(公告)号：US20070083732A1

    公开(公告)日：2007-04-12

    申请号：US11591754

    申请日：2006-11-01

    申请人： Shinichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama ,  Kazuhiko Iwanaga ,  Hiroshi Takafuji

    发明人： Shinichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama ,  Kazuhiko Iwanaga ,  Hiroshi Takafuji

    IPC分类号： G06F15/00

    CPC分类号： G06F15/8007

    摘要： A parallel processor includes a global processor which interprets a program and control controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data. The global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.

    摘要翻译： 并行处理器包括解释程序和控制整个并行处理器的全局处理器。 处理器元件块包括多个处理器元件，每个处理器元件包括用于处理多组数据的寄存器文件和操作阵列。 全局处理器向多个处理器元件输出控制信号，并且由此分别将对应于多个处理器元件的处理器单元号码设置为操作数组的输入值。

    Single instruction stream multiple data stream processor
    8.
    发明授权
    Single instruction stream multiple data stream processor 有权
    单指令流多数据流处理器

    公开(公告)号：US06785800B1

    公开(公告)日：2004-08-31

    申请号：US09658860

    申请日：2000-09-08

    申请人： Shin-ichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama ,  Kazuhiko Iwanaga ,  Hiroshi Takafuji

    发明人： Shin-ichi Yamaura ,  Kazuhiko Hara ,  Takao Katayama ,  Kazuhiko Iwanaga ,  Hiroshi Takafuji

    IPC分类号： G06F1580

    CPC分类号： G06F15/8007

    摘要： A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit, a data transfer bus interconnecting with other PEs, and a register controller for inputting a read or write signal to the register. Read and write processing steps in the processor are carried out by the register controller in response to the signals which are sent form the register controller and inputted into a register of specific processor elements responding to an addressing signal from an external interface. The processor is capable of transferring data directly to a specific processor element, thereby achieving higher speeds of data transfer and resultant data processing and makes flexible use of registers to thereby attain efficient data processing utilizing arbitrary combinations of the register depending on bit width of the data.

    摘要翻译： SIMD处理器包括多个具有用于数据处理的处理单元的处理器元件（PE），用于保持待处理或由处理单元处理的数据的寄存器，与其它PE互连的数据传输总线，以及用于输入的寄存器控制器 读或写信号到寄存器。 处理器中的读和写处理步骤由寄存器控制器响应于从寄存器控制器发送并被输入到来自外部接口的寻址信号的特定处理器元件的寄存器中的信号来执行。 处理器能够将数据直接传送到特定的处理器元件，从而实现更高的数据传输速度和最终的数据处理，并灵活地使用寄存器，从而根据数据的位宽来利用寄存器的任意组合来实现有效的数据处理 。