公开(公告)号：US10468535B2

公开(公告)日：2019-11-05

申请号：US13636255

申请日：2011-04-07

申请人： Shinya Morita ,  Toshihiro Kugimiya ,  Takeaki Maeda ,  Satoshi Yasuno ,  Yasuaki Terao ,  Aya Miki

发明人： Shinya Morita ,  Toshihiro Kugimiya ,  Takeaki Maeda ,  Satoshi Yasuno ,  Yasuaki Terao ,  Aya Miki

IPC分类号： C23C14/34 ,  H01L29/786 ,  H01L21/02 ,  C23C14/08

摘要： Disclosed is an oxide for a semiconductor layer of a thin film transistor, which, when used in a thin film transistor that includes an oxide semiconductor in the semiconductor layer, imparts good switching characteristics and stress resistance to the transistor. Specifically disclosed is an oxide for a semiconductor layer of a thin film transistor, which is used for a semiconductor layer of a thin film transistor and contains at least one element selected from the group consisting of In, Ga and Zn and at least one element selected from the group X consisting of Al, Si, Ni, Ge, Sn, Hf, Ta and W.

公开(公告)号：US20130009111A1

公开(公告)日：2013-01-10

申请号：US13636255

申请日：2011-04-07

申请人： Shinya Morita ,  Toshihiro Kugiyama ,  Takeaki Maeda ,  Satoshi Yasuno ,  Yasuaki Terao ,  Aya Miki

发明人： Shinya Morita ,  Toshihiro Kugiyama ,  Takeaki Maeda ,  Satoshi Yasuno ,  Yasuaki Terao ,  Aya Miki

IPC分类号： H01B1/08 ,  C01G35/00 ,  C01G17/00 ,  C01G41/02 ,  C23C14/14 ,  C01B33/20 ,  C01G27/02 ,  C01G19/02 ,  C01G9/02 ,  C01G53/04 ,  C01G15/00

CPC分类号： H01L29/7869 ,  C23C14/08 ,  C23C14/3414 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631

摘要： Disclosed is an oxide for a semiconductor layer of a thin film transistor, which, when used in a thin film transistor that includes an oxide semiconductor in the semiconductor layer, imparts good switching characteristics and stress resistance to the transistor. Specifically disclosed is an oxide for a semiconductor layer of a thin film transistor, which is used for a semiconductor layer of a thin film transistor and contains at least one element selected from the group consisting of In, Ga and Zn and at least one element selected from the group X consisting of Al, Si, Ni, Ge, Sn, Hf, Ta and W.

摘要翻译： 公开了一种用于薄膜晶体管的半导体层的氧化物，当在包括半导体层中的氧化物半导体的薄膜晶体管中使用时，对晶体管赋予良好的开关特性和耐应力性。 具体公开了用于薄膜晶体管的半导体层的氧化物，其用于薄膜晶体管的半导体层，并且包含选自由In，Ga和Zn组成的组中的至少一种元素和至少一种元素选择 从由Al，Si，Ni，Ge，Sn，Hf，Ta和W组成的组X

公开(公告)号：US20140319512A1

公开(公告)日：2014-10-30

申请号：US14113322

申请日：2012-04-19

申请人： Takeaki Maeda ,  Toshihiro Kugimiya ,  Jun Ho Song ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

发明人： Takeaki Maeda ,  Toshihiro Kugimiya ,  Jun Ho Song ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC分类号： H01L29/786 ,  H01L27/12

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L27/1222 ,  H01L29/78693

摘要： There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains Sn and at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer.

摘要翻译： 提供了一种氧化物半导体层，当在有机EL显示器和液晶显示器等显示装置中沉积钝化层等时，能够使薄膜晶体管的电特性稳定，而不需要氧化处理层。 本发明的薄膜晶体管结构至少在衬底上具有氧化物半导体层，源 - 漏电极和钝化层，从衬底侧开始，其中氧化物半导体层是 第一氧化物半导体层和第二氧化物半导体层; 第一氧化物半导体层的Zn含量占所有金属元素的百分比为50原子％以上，第一氧化物半导体层形成在源 - 漏电极和钝化层侧; 所述第二氧化物半导体层含有Sn和选自In，Ga和Zn中的至少一种元素，并且所述第二氧化物半导体层形成在所述基板侧; 并且第一氧化物半导体层与源 - 漏电极和钝化层直接接触。

公开(公告)号：US09093542B2

公开(公告)日：2015-07-28

申请号：US14113322

申请日：2012-04-19

申请人： Takeaki Maeda ,  Toshihiro Kugimiya ,  Jun Ho Song ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

发明人： Takeaki Maeda ,  Toshihiro Kugimiya ,  Jun Ho Song ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC分类号： H01L29/10 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/12

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L27/1222 ,  H01L29/78693

摘要： There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains Sn and at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer.

摘要翻译： 提供了一种氧化物半导体层，当在有机EL显示器和液晶显示器等显示装置中沉积钝化层等时，能够使薄膜晶体管的电特性稳定，而不需要氧化处理层。 本发明的薄膜晶体管结构至少在衬底上具有氧化物半导体层，源 - 漏电极和钝化层，从衬底侧开始，其中氧化物半导体层是 第一氧化物半导体层和第二氧化物半导体层; 第一氧化物半导体层的Zn含量占所有金属元素的百分比为50原子％以上，第一氧化物半导体层形成在源 - 漏电极和钝化层侧; 所述第二氧化物半导体层含有Sn和选自In，Ga和Zn中的至少一种元素，并且所述第二氧化物半导体层形成在所述基板侧; 并且第一氧化物半导体层与源 - 漏电极和钝化层直接接触。

公开(公告)号：US09379248B2

公开(公告)日：2016-06-28

申请号：US14113303

申请日：2012-04-19

申请人： Takeaki Maeda ,  Toshihiro Kugimiya

发明人： Takeaki Maeda ,  Toshihiro Kugimiya

IPC分类号： H01L29/786 ,  G02F1/1368 ,  H01L27/12

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L27/1222 ,  H01L29/78693

摘要： There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays depositing and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer.

摘要翻译： 提供了一种氧化物半导体层，当在有机EL显示器沉积和液晶显示器等显示装置中沉积钝化层等时，能够使薄膜晶体管的电特性稳定，而不需要氧化处理层。 本发明的薄膜晶体管结构至少在衬底上具有氧化物半导体层，源 - 漏电极和钝化层，从衬底侧开始，其中氧化物半导体层是 第一氧化物半导体层和第二氧化物半导体层; 第一氧化物半导体层的Zn含量占所有金属元素的百分比为50原子％以上，第一氧化物半导体层形成在源 - 漏电极和钝化层侧; 所述第二氧化物半导体层含有选自In，Ga和Zn中的至少一种元素，并且所述第二氧化物半导体层形成在所述基板侧; 并且第一氧化物半导体层与源 - 漏电极和钝化层直接接触。

公开(公告)号：US20130228926A1

公开(公告)日：2013-09-05

申请号：US13882635

申请日：2011-10-11

申请人： Takeaki Maeda ,  Toshihiro Kugimiya

发明人： Takeaki Maeda ,  Toshihiro Kugimiya

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L27/1225 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is an interconnection structure that, in a display device such as an organic EL display or a liquid crystal display, has superior workability during wet etching even without providing an etch stop layer. The interconnection structure has, in the given order, a substrate, a semiconductor layer of a thin film transistor, and a metal interconnection film, and has a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer comprises an oxide semiconductor, the barrier layer has a layered structure of a high-melting-point metal thin film and a Si thin film, and the Si thin film is directly connected to the semiconductor layer.

摘要翻译： 提供一种在诸如有机EL显示器或液晶显示器的显示装置中即使不提供蚀刻停止层也在湿法蚀刻期间具有优异的可加工性的互连结构。 互连结构按照给定的顺序具有衬底，薄膜晶体管的半导体层和金属互连膜，并且在半导体层和金属互连膜之间具有阻挡层。 半导体层包括氧化物半导体，阻挡层具有高熔点金属薄膜和Si薄膜的层叠结构，并且Si薄膜直接连接到半导体层。

公开(公告)号：US20130181218A1

公开(公告)日：2013-07-18

申请号：US13877065

申请日：2011-09-30

申请人： Takeaki Maeda ,  Toshihiro Kugimiya

发明人： Takeaki Maeda ,  Toshihiro Kugimiya

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  G02F1/1368 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure includes a semiconductor layer of a thin-film transistor and a metal interconnection film above a substrate in this order from a side of the substrate, and includes a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer is composed of an oxide semiconductor. The barrier layer is composed of a Ti oxide film containing TiOx (where x is from 1.0 to 2.0), and the Ti oxide film is directly connected to the semiconductor layer. The oxide semiconductor is composed of an oxide containing at least one element selected from the group consisting of In, Ga, Zn and Sn.

摘要翻译： 互连结构从衬底侧依次包括薄膜晶体管的半导体层和金属互连膜，并且在半导体层和金属互连膜之间包括阻挡层。 半导体层由氧化物半导体构成。 阻挡层由含有TiOx（x为1.0〜2.0）的Ti氧化物膜构成，Ti氧化膜与半导体层直接连接。 氧化物半导体由含有选自In，Ga，Zn和Sn中的至少一种元素的氧化物构成。

公开(公告)号：US09153536B2

公开(公告)日：2015-10-06

申请号：US14117531

申请日：2012-05-16

申请人： Hiroyuki Okuno ,  Toshihiro Kugimiya ,  Yoshihiro Yokota ,  Takeaki Maeda

发明人： Hiroyuki Okuno ,  Toshihiro Kugimiya ,  Yoshihiro Yokota ,  Takeaki Maeda

IPC分类号： H01L29/15 ,  H01L29/22 ,  H01L31/0256 ,  H01L31/0296 ,  H01L23/532 ,  H01J37/34 ,  C22C21/02 ,  C22C21/00 ,  C22C21/12 ,  C22C21/14 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L23/53219 ,  C22C21/00 ,  C22C21/02 ,  C22C21/12 ,  C22C21/14 ,  C22F1/04 ,  C23C14/165 ,  C23C14/3414 ,  H01J37/3429 ,  H01L21/2855 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/452 ,  H01L2924/0002 ,  Y10T428/12431 ,  H01L2924/00

摘要： Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high temperatures, and which has low electrical resistivity as a film. The present invention relates to an Al alloy film for semiconductor devices, which is characterized by satisfying all of the features (a)-(c) described below after being subjected to a heat treatment wherein the Al alloy film is held at 500° C. for 30 minutes and by having a film thickness from 500 nm to 5 μm. (a) The maximum grain diameter of the Al matrix is 800 nm or less. (b) The hillock density is less than 1×109 pieces/m2. (c) The electrical resistivity is 10 μΩcm or less.

摘要翻译： 提供一种用于半导体器件的Al合金膜，其耐热性优异，并且即使在Al合金膜暴露于高温的情况下也能抑制小丘的产生，并且作为膜具有低电阻率。 本发明涉及一种用于半导体器件的Al合金膜，其特征在于，在将Al合金膜保持在500℃进行热处理之后，满足下述所有特征（a） - （c） 30分钟，膜厚500nm〜5μm。 （a）Al基体的最大粒径为800nm以下。 （b）小丘密度小于1×109个/ m2。 （c）电阻率为10μΩ·cm以上。

公开(公告)号：US20150171016A1

公开(公告)日：2015-06-18

申请号：US14117531

申请日：2012-05-16

申请人： Hiroyuki Okuno ,  Toshihiro Kugimiya ,  Yoshihiro Yokota ,  Takeaki Maeda

发明人： Hiroyuki Okuno ,  Toshihiro Kugimiya ,  Yoshihiro Yokota ,  Takeaki Maeda

IPC分类号： H01L23/532 ,  C22C21/02 ,  H01L29/20 ,  C22C21/12 ,  C22C21/14 ,  H01L29/16 ,  H01J37/34 ,  C22C21/00

CPC分类号： H01L23/53219 ,  C22C21/00 ,  C22C21/02 ,  C22C21/12 ,  C22C21/14 ,  C22F1/04 ,  C23C14/165 ,  C23C14/3414 ,  H01J37/3429 ,  H01L21/2855 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/452 ,  H01L2924/0002 ,  Y10T428/12431 ,  H01L2924/00

摘要： Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high temperatures, and which has low electrical resistivity as a film. The present invention relates to an Al alloy film for semiconductor devices, which is characterized by satisfying all of the features (a)-(c) described below after being subjected to a heat treatment wherein the Al alloy film is held at 500° C. for 30 minutes and by having a film thickness from 500 nm to 5 μm. (a) The maximum grain diameter of the Al matrix is 800 nm or less. (b) The hillock density is less than 1×109 pieces/m2. (c) The electrical resistivity is 10 μΩcm or less.

摘要翻译： 提供一种用于半导体器件的Al合金膜，其耐热性优异，并且即使在Al合金膜暴露于高温的情况下也能抑制小丘的产生，并且作为膜具有低电阻率。 本发明涉及一种用于半导体器件的Al合金膜，其特征在于，在将Al合金膜保持在500℃进行热处理之后，满足下述所有特征（a） - （c） 30分钟，膜厚500nm〜5μm。 （a）Al基体的最大粒径为800nm以下。 （b）小丘密度小于1×109个/ m2。 （c）电阻率为10μΩ·cm以上。

公开(公告)号：US20140054588A1

公开(公告)日：2014-02-27

申请号：US14113303

申请日：2012-04-19

申请人： Takeaki Maeda ,  Toshihiro Kugimiya

发明人： Takeaki Maeda ,  Toshihiro Kugimiya

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L27/1222 ,  H01L29/78693

摘要： There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays depositing and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer.

摘要翻译： 提供了一种氧化物半导体层，当在有机EL显示器沉积和液晶显示器等显示装置中沉积钝化层等时，能够使薄膜晶体管的电特性稳定，而不需要氧化处理层。 本发明的薄膜晶体管结构至少在衬底上具有氧化物半导体层，源 - 漏电极和钝化层，从衬底侧开始，其中氧化物半导体层是 第一氧化物半导体层和第二氧化物半导体层; 第一氧化物半导体层的Zn含量占所有金属元素的百分比为50原子％以上，第一氧化物半导体层形成在源 - 漏电极和钝化层侧; 所述第二氧化物半导体层含有选自In，Ga和Zn中的至少一种元素，并且所述第二氧化物半导体层形成在所述基板侧; 并且第一氧化物半导体层与源 - 漏电极和钝化层直接接触。