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    Data processing apparatus and compiler apparatus
    1.
    发明申请
    Data processing apparatus and compiler apparatus 审中-公开
    数据处理装置和编译装置

    公开(公告)号：US20050144420A1

    公开(公告)日：2005-06-30

    申请号：US10995148

    申请日：2004-11-24

    申请人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

    发明人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

    IPC分类号： G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

    CPC分类号： G06F9/342 ,  G06F8/4442 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0888 ,  G06F2212/6028

    摘要： The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.

    摘要翻译： 能够有效地使用高速缓冲存储器的数据处理装置包括：高速缓存存储器28和存储由物理地址指定的每个区域中的指令或数据的存储器30; 输出包括表示规定处理的物理地址和处理确定数据的逻辑地址的算术处理单元22，获得与包含在逻辑地址中的物理地址相对应的指令或数据，并执行指令; 地址转换单元26，其将由运算处理单元22输出的逻辑地址转换成物理地址。 数据处理装置读取存储在高速缓冲存储器28和存储器30中由物理地址指定的区域中的指令或数据，并根据处理确定数据执行规定的处理。

    Compiler apparatus for optimizing high-level language programs using directives
    2.
    发明授权
    Compiler apparatus for optimizing high-level language programs using directives 有权
    用于使用指令优化高级语言程序的编译器设备

    公开(公告)号：US07571432B2

    公开(公告)日：2009-08-04

    申请号：US10944831

    申请日：2004-09-21

    申请人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

    发明人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

    IPC分类号： G06F9/45

    CPC分类号： G06F8/4442

    摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

    摘要翻译： 编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。 该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。 上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

    Compiler apparatus
    3.
    发明申请
    Compiler apparatus 有权
    编译器

    公开(公告)号：US20050086653A1

    公开(公告)日：2005-04-21

    申请号：US10944831

    申请日：2004-09-21

    申请人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

    发明人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

    IPC分类号： G06F9/45

    CPC分类号： G06F8/4442

    摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

    摘要翻译： 编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。 该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。 上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

    Computer system, compiler apparatus, and operating system
    4.
    发明授权
    Computer system, compiler apparatus, and operating system 有权
    计算机系统，编译器和操作系统

    公开(公告)号：US07424578B2

    公开(公告)日：2008-09-09

    申请号：US10885708

    申请日：2004-07-08

    申请人： Kiyoshi Nakashima ,  Taketo Heishi ,  Shohei Michimoto

    发明人： Kiyoshi Nakashima ,  Taketo Heishi ,  Shohei Michimoto

    IPC分类号： G06F9/38

    CPC分类号： G06F8/4442 ,  G06F12/0862 ,  G06F2212/6028

    摘要： A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.

    摘要翻译： 一种用于能够提高高速缓冲存储器的命中率的计算机系统的编译装置，其包括预取目标提取装置，线程激活处理插入装置和线程处理创建装置。 编译器设备创建用于执行预取和预清理的线程。 通过考虑节目优先级和高速缓冲存储器的使用率，由该编译装置创建的预取和预擦写线程与主节目的操作并行执行预取和预清除。

    Computer system, compiler apparatus, and operating system
    5.
    发明申请
    Computer system, compiler apparatus, and operating system 有权
    计算机系统，编译器和操作系统

    公开(公告)号：US20050071572A1

    公开(公告)日：2005-03-31

    申请号：US10885708

    申请日：2004-07-08

    申请人： Kiyoshi Nakashima ,  Taketo Heishi ,  Shohei Michimoto

    发明人： Kiyoshi Nakashima ,  Taketo Heishi ,  Shohei Michimoto

    IPC分类号： G06F9/45 ,  G06F9/46 ,  G06F12/08 ,  G06F15/16 ,  G06F12/00

    CPC分类号： G06F8/4442 ,  G06F12/0862 ,  G06F2212/6028

    摘要： A complier apparatus for a computer system that is capable of improving the hit rate of a cache memory is comprised of a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device, and creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.

    摘要翻译： 能够提高高速缓存存储器的命中率的计算机系统的编译器装置由预取目标提取装置，线程激活处理插入装置和线程进程创建装置组成，并且创建用于执行预取和预清除的线程 。 通过考虑节目优先级和高速缓冲存储器的使用率，由该编译装置创建的预取和预擦写线程与主节目的操作并行执行预取和预清除。