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公开(公告)号：US20050144420A1
公开(公告)日：2005-06-30
申请号：US10995148
申请日：2004-11-24
申请人： Shohei Michimoto , Hajime Ogawa , Taketo Heishi , Kiyoshi Nakashima , Hazuki Okabayashi , Ryuta Nakanishi
发明人： Shohei Michimoto , Hajime Ogawa , Taketo Heishi , Kiyoshi Nakashima , Hazuki Okabayashi , Ryuta Nakanishi
CPC分类号： G06F9/342 , G06F8/4442 , G06F9/383 , G06F12/0862 , G06F12/0888 , G06F2212/6028
摘要： The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.
摘要翻译： 能够有效地使用高速缓冲存储器的数据处理装置包括：高速缓存存储器28和存储由物理地址指定的每个区域中的指令或数据的存储器30; 输出包括表示规定处理的物理地址和处理确定数据的逻辑地址的算术处理单元22，获得与包含在逻辑地址中的物理地址相对应的指令或数据，并执行指令; 地址转换单元26，其将由运算处理单元22输出的逻辑地址转换成物理地址。 数据处理装置读取存储在高速缓冲存储器28和存储器30中由物理地址指定的区域中的指令或数据，并根据处理确定数据执行规定的处理。
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公开(公告)号：US07502887B2
公开(公告)日：2009-03-10
申请号：US10578314
申请日：2004-09-08
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Ryuta Nakanishi , Tokuzo Kiyohara , Takao Yamamoto , Keisuke Kaneko
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Ryuta Nakanishi , Tokuzo Kiyohara , Takao Yamamoto , Keisuke Kaneko
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/121 , G06F12/126
摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.
摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。
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公开(公告)号：US20080168232A1
公开(公告)日：2008-07-10
申请号：US10577133
申请日：2004-11-02
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/121
摘要： A cache memory according to the present invention includes: a W flag setting unit (40) that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order; and a replace unit (39) that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
摘要翻译： 根据本发明的缓存存储器包括：W标志设置单元，其修改指示保存高速缓存的数据单元的每个高速缓存条目的访问顺序的顺序数据，以便反映实际的访问顺序; 以及替换单元（39），其基于修改的订单数据选择用于替换的高速缓存条目并替换高速缓存条目。
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公开(公告)号：US20070143548A1
公开(公告)日：2007-06-21
申请号：US10583773
申请日：2004-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。
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公开(公告)号：US07555610B2
公开(公告)日：2009-06-30
申请号：US10578299
申请日：2004-11-02
IPC分类号： G06F13/00
CPC分类号： G06F12/126
摘要： The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit 39 which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.
摘要翻译： 本发明的高速缓冲存储器包括：C标志设置单元40，其向每个高速缓存条目保持行数据添加指示以后将执行写入操作的清除标志C;以及清除单元39， 向存储器提供已经添加了指示不执行写入操作的清除标志C的高速缓存条目的行数据，并且已经设置了指示已经写入高速缓存条目的脏标志D。
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公开(公告)号：US20090100231A1
公开(公告)日：2009-04-16
申请号：US11816858
申请日：2006-02-08
IPC分类号： G06F12/08
CPC分类号： G06F12/12 , G06F12/0802 , G06F12/0893
摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。
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公开(公告)号：US20090077318A1
公开(公告)日：2009-03-19
申请号：US11910831
申请日：2006-03-17
申请人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0888
摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。
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公开(公告)号：US07454575B2
公开(公告)日：2008-11-18
申请号：US10583773
申请日：2004-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。
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公开(公告)号：US20070186048A1
公开(公告)日：2007-08-09
申请号：US10599170
申请日：2005-03-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line data, from the memory to the cache memory; and a touch unit 415 which sets the predicted line address to the cache entry, as a tag, and validates the valid flag, without loading data from the memory into the cache memory
摘要翻译： 本发明的高速缓冲存储器包括：预测单元39，其基于从存储器输出的存储器访问的进度，预测下一个预取的行地址。 预测单元39包括：预取单元414，其将预测行数据的数据从存储器预取到高速缓冲存储器; 以及触摸单元415，其将预测线路地址设置为高速缓存条目作为标签，并且验证有效标志，而不将数据从存储器加载到高速缓冲存储器
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公开(公告)号：US07953935B2
公开(公告)日：2011-05-31
申请号：US11816858
申请日：2006-02-08
IPC分类号： G06F13/00
CPC分类号： G06F12/12 , G06F12/0802 , G06F12/0893
摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。
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