公开(公告)号：US4835790A

公开(公告)日：1989-05-30

申请号：US210657

申请日：1988-06-23

申请人： Shousei Yoshida ,  Susumu Otani ,  Toshiya Todoroki

发明人： Shousei Yoshida ,  Susumu Otani ,  Toshiya Todoroki

IPC分类号： G01R29/26 ,  H04B17/00 ,  H04L27/00 ,  H04L27/227

CPC分类号： H04L27/2273 ,  G01R29/26 ,  H04B17/20 ,  H04L2027/0016 ,  H04L2027/0067 ,  H04L2027/0075

摘要： A carrier-to-noise detector comprises an A/D converter (1) which samples an output of the demodulator of a digital transmission system at a symbol clock rate and converting it to a digital signal having positive and negative values. An absolute value converting circuit (2) converts the output of A/D converter into an absolute value which is averaged by a first averaging circuit (3) over a period sufficient to suppress short term variations and then squared by a first squaring circuit (4) to give an output representing the carrier component. The output of A/D converter is, on the other hand, squared by a second squaring circuit (5) and averaged by a second averaging circuit (6) to suppress short term variations to give an output representing a total of the carrier and noise components. The carrier component in the output of the second averaging circuit 6 is subtracted by a subtractor (7). A ratio between the outputs of the first squaring circuit (4) and subtracting circuit (7) is derived by a divider (8) as a representation of a carrier-to-noise ratio.

摘要翻译： 载波噪声检测器包括A / D转换器（1），其以符号时钟速率对数字传输系统的解调器的输出进行采样，并将其转换为具有正值和负值的数字信号。 绝对值转换电路（2）将A / D转换器的输出转换为绝对值，该绝对值由第一平均电路（3）在足以抑制短期变化的时间内平均，然后由第一平方电路（4 ）来给出表示载波分量的输出。 另一方面，A / D转换器的输出由第二平方电路（5）平方并由第二平均电路（6）平均，以抑制短期变化，从而给出表示载波和噪声的总和的输出 组件。 第二平均电路6的输出中的载波分量由减法器（7）减去。 第一平方电路（4）和减法电路（7）的输出之间的比值由分频器（8）导出为载波噪声比的表示。

公开(公告)号：US4780887A

公开(公告)日：1988-10-25

申请号：US87319

申请日：1987-08-20

申请人： Susumu Otani ,  Yoshio Tanimoto ,  Shousei Yoshida

发明人： Susumu Otani ,  Yoshio Tanimoto ,  Shousei Yoshida

IPC分类号： H04L27/227 ,  H04L27/14

CPC分类号： H04L27/2277

摘要： A carrier recovery circuit comprises first and second mixers for mixing a received PSK signal with first and second reference frequency signals. A remodulator extracts a preamble from each burst of the PSK signal and supplies the extracted carrier to a carrier recovery means to cause it to derive a reference carrier from the extracted preamble. A phase detector is connected to the outputs of the first and second mixers for detecting a phase difference between the PSK signal and the reference carrier, the detected phase difference being applied to a resettable noise reduction circuit for reducing amplitude fluctuations contained in the phase difference, the noise reduction circuit being arranged to be reset in response to each of the bursts to discharge energy stored as a result of the noise reduction and eliminate interburst phase errors which occur as a result of interburst frequency variations. A variable phase shifter controls the phase of the reference carrier in accordance with the output of the noise eliminator and supplies quadrature versions of the phase controlled carrier to the first and second mixers as the first and second reference frequency signals.

公开(公告)号：US4891598A

公开(公告)日：1990-01-02

申请号：US241669

申请日：1988-09-08

申请人： Shousei Yoshida ,  Susumu Otani

发明人： Shousei Yoshida ,  Susumu Otani

IPC分类号： H04L7/027 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22

CPC分类号： H04L7/0334

摘要： In a variable bit rate clock recovery circuit, a phase difference between an input demodulated signal and a recovered clock signal is detected, the detected phase difference signal is filtered by a loop filter and is then integrated, the integrated signal is supplied as an address to first and second ROMs, which store data of cosine and sine waves in advance, output data from the first and second ROMs are respectively D/A-converted by first and second D/A converters, an output signal from a variable frequency generator is modulated by using an output from the first D/A converter, a signal obtained by shifting the output signal from the variable frequency signal generator by .pi./2 radians is modulated by an output from the second D/A converter, and the respective modulated signals are synthesized, thereby obtaining a reference clock signal.

公开(公告)号：US5073906A

公开(公告)日：1991-12-17

申请号：US624201

申请日：1990-12-06

申请人： Susumu Otani ,  Syouji Endo

发明人： Susumu Otani ,  Syouji Endo

IPC分类号： H04L7/08 ,  H04L7/02 ,  H04L7/04

CPC分类号： H04L7/042

摘要： A synchronization (sync) word detection apparatus which, on receiving a signal in which a sync word having a predetermined length (N) is inserted beforehand, detects the sync word out of a demodulated and soft-decided sequence of the received signal. A cross correlator (4) calculates a cross correlation value of the soft-decided and demodulated sequence fed thereto and the sync word. A threshold generating section (1, 2, 3) determines a means power of the demodulated and soft-decided sequence and generates a threshold value on the basis of the mean power. A comparing circuit (5) produces a detection signal when the cross correlation exceeds the threshold value. The apparatus reduces the false detection probability and misdetection prbability even when the receive field intensity sharply changes on a transmission path.

公开(公告)号：US4871975A

公开(公告)日：1989-10-03

申请号：US289617

申请日：1988-12-23

申请人： Hizuru Nawata ,  Susumu Otani

发明人： Hizuru Nawata ,  Susumu Otani

IPC分类号： H04L27/38 ,  H04L7/04 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227

CPC分类号： H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0057 ,  H04L2027/0069 ,  H04L7/046

摘要： A carrier recovery circuit comprises a voltage-controlled oscillator with a .pi./2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at .pi./4, (3/4).pi., (5/4).pi. and (7/4).pi. radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected. To stabilize the operation of the carrier recovery loop of the circuit, the output of the second phase comparator from which that BTR is detected is briefly applied to the loop filter in response to the detection of a BTR of the second channel, instead of the signal from the quadri-phase detector.

公开(公告)号：US4853642A

公开(公告)日：1989-08-01

申请号：US213368

申请日：1988-06-30

申请人： Susumu Otani ,  Motoya Iwasaki

发明人： Susumu Otani ,  Motoya Iwasaki

IPC分类号： H03L7/12 ,  H04L27/00 ,  H04L27/227

CPC分类号： H04L27/2273 ,  H03L7/12 ,  H04L2027/0067 ,  H04L2027/0069 ,  Y10S331/02

摘要： In a phase controlled demodulator, a modulated digital input signal is demodulated into quadrature signals with a carrier recovered by a voltage controlled oscillator. A phase difference between the quadrature signals is detected by a phase detector of Costas loop and applied through a loop filter to the voltage controlled oscillator to control the frequency and phase of the recovered carrier when the frequency deviation between the received and recovered carriers is within a phase control range. When the frequency deviation exceeds the phase control range, the output of the phase detector is a beat of the two carriers and a frequency sweep control voltage is applied to the VCO to search for the missing carrier. The magnitude of the beat is detected and compared with a predetermined threshold value. When the frequency deviation is far beyond the control range, the magnitude of the beat is lower than the threshold, but exceeds it at the instant the demodulator enters the control range, whereupon the frequency sweep control voltage is removed from the VCO.

公开(公告)号：US4097813A

公开(公告)日：1978-06-27

申请号：US803900

申请日：1977-06-06

申请人： Susumu Otani ,  Toshitake Noguchi

发明人： Susumu Otani ,  Toshitake Noguchi

IPC分类号： H04L27/10 ,  H04L27/227 ,  H03K9/00

CPC分类号： H04L27/2276

摘要： A circuit for extracting a carrier wave signal from a double binary PSK signal input is disclosed. The PSK input signal is applied to a first frequency doubler which doubles the frequency of the input signal. The output of the first frequency doubler is applied to a second frequency doubler and to first and second band-pass filter circuits. The second frequency doubler serves to quadruple the frequency of the PSk input signal and derives a signal having a line spectrum at the frequency 4fc whenever there is no phase shift between successive time slots of the PSK signal. The first and second band-pass filters derive first and second signals having line spectra at frequencies 2fc + fs and 2fc - fs, respectively, whenever there is a phase shift of +90.degree. or -90.degree., respectively, between successive time slots of the PSK input signal. The outputs of the band-pass filter circuits are combined in first and second frequency mixers with a clock frequency signal which is synchronized with the clock frequency component of the input signal. The outputs of the frequency mixers are combined in a first signal combiner circuit whose output is applied to third frequency doubler. The output of the third frequency doubler has a line spectrum at 4fc whenever there is a .+-. 90.degree. phase shift between successive time slots of the PSK input signal. The outputs of the first and third frequency doublers are combined in a second signal combiner and applied to a carrier wave synchronizing circuit which derives the desired synchronized carrier wave.

摘要翻译： 公开了一种从双二进制PSK信号输入端提取载波信号的电路。 PSK输入信号被施加到将输入信号的频率加倍的第一倍频器。 第一倍频器的输出被施加到第二倍频器和第一和第二带通滤波器电路。 当PSK信号的连续时隙之间没有相移时，第二倍频器用于使PSk输入信号的频率增加四倍，并且导出具有频率为4fc的线谱的信号。 第一和第二带通滤波器分别衍生具有频率为2fc + fs和2fc-fs的线谱的第一和第二信号，每当在相继的时隙之间存在+90°或-90°的相移时， PSK输入信号。 带通滤波器电路的输出在第一和第二混频器中与与输入信号的时钟频率分量同步的时钟频率信号组合。 混频器的输出组合在第一信号组合器电路中，其输出被施加到第三倍频器。 当PSK输入信号的连续时隙之间存在+/- 90°相移时，第三倍频器的输出具有4fc的线谱。 第一和第三频率倍增器的输出在第二信号组合器中组合，并被应用于导出期望的同步载波的载波同步电路。

公开(公告)号：US5245612A

公开(公告)日：1993-09-14

申请号：US643793

申请日：1991-01-22

申请人： Seiji Kachi ,  Susumu Otani ,  Motoya Iwasaki ,  Shoji Endo ,  Shinichi Kono

发明人： Seiji Kachi ,  Susumu Otani ,  Motoya Iwasaki ,  Shoji Endo ,  Shinichi Kono

IPC分类号： H04B7/216

CPC分类号： H04B7/216

摘要： A satellite packet communication system comprising a central station and VSAT stations. The central station generates chip-rate clock pulses and transmits a series of data on timeslots of a frame to a satellite transponder, and a plurality of terminal stations. Each VSAT station receives the frame from the transponder and recovers the chip-rate clock pulses from the received frame. A pseudorandom number (PN) sequence generator, provided in the terminal station is synchronized with the recovered chip-rate clock pulses for generating bits of a PN sequence with which packetized data bits are pseudorandomly modulated and transmitted in burst form to the transponder. The central station includes a correlator which is synchronized with the central station's chip-rate clock pulses to detect correlations between the pseudorandomly modulated data bits a sequence of pseudorandom numbers corresponding to the PN sequence bits of the terminal stations.

摘要翻译： 一种包括中心站和VSAT站的卫星分组通信系统。 中心站产生码片速率时钟脉冲，并将一帧数据发送到卫星转发器和多个终端站。 每个VSAT站从应答器接收帧并从接收帧恢复码片速率时钟脉冲。 在终端站中提供的伪随机数（PN）序列发生器与恢复的码片速率时钟脉冲同步，用于产生PN序列的比特，以分组形式的数据比特被伪随机调制并以突发形式发送到应答器。 中央站包括相关器，其与中心站的芯片速率时钟脉冲同步，以检测伪随机调制数据位之间与终端站的PN序列比特对应的伪随机数序列的相关性。

公开(公告)号：US4606027A

公开(公告)日：1986-08-12

申请号：US659533

申请日：1984-10-10

申请人： Susumu Otani

发明人： Susumu Otani

IPC分类号： H03M13/23 ,  H03M13/41 ,  G06F11/10

CPC分类号： H03M13/395 ,  H03M13/41

摘要： In an error correcting apparatus, an add-compare-select circuit is provided for each state in a given time slot of a Viterbi trellis diagram. The ACS circuit includes first and second pairs of adders coupled to a source of sequentially updated path metrics and to a branch metric generator which generates sums of branch metrics over successive time slots. The updated path metrics of states two time slots prior to the given time slot and the branch metric sums are added up in the adders. The outputs of adders in pairs are compared respectively by first comparators to determine the highest of the adder outputs. The determined highest values are passed through first selectors to a second comparator to further determine the highest of the selected adder outputs, the further determined value being passed through a second selector to the path metric source to update the previous value. Control signals indicating the determinations taken by the first and second comparators are coupled to a path memory for storing data indicating the paths of the selected values.

摘要翻译： 在纠错装置中，在维特比网格图的给定时隙中为每个状态提供加法比较选择电路。 ACS电路包括耦合到顺序更新的路径度量的源的第一和第二对加法器以及在连续时隙上产生分支度量的和的分支度量发生器。 给定时隙之前的两个时隙的状态的更新的路径度量和分支度量总和在加法器中相加。 成对加法器的输出通过第一比较器进行比较，以确定加法器输出的最高值。 所确定的最高值通过第一选择器传递到第二比较器，以进一步确定所选择的加法器输出中的最高值，进一步确定的值通过第二选择器传递到路径度量源以更新先前值。 指示由第一和第二比较器取得的确定的控制信号被耦合到路径存储器，用于存储指示所选值的路径的数据。

公开(公告)号：US4064598A

公开(公告)日：1977-12-27

申请号：US652992

申请日：1976-01-28

申请人： Takashi Katoh ,  Susumu Otani

发明人： Takashi Katoh ,  Susumu Otani

IPC分类号： D01G15/42 ,  D01G15/80 ,  D01G15/40 ,  D01G15/82

CPC分类号： D01G15/805 ,  D01G15/42

摘要： In a high production card, a taker-in undercasing without slits or apertures is disposed beneath a taker-in roller of a card and a suction device is disposed above the taker-in roller. A taker-in cover is mounted atop the taker-in roller and defines therebetween a sealed space in communication with the suction device, which suction device controls the air pressure in said space between the taker-in roller and the taker-in undercasing, so that impurities such as trash are mainly removed from the supplied fibers at a free space below the taker-in roller formed at a position upstream from the taker-in undercasing, and short fibers are separated from successive fibers mainly by the action of the suction device.

摘要翻译： 在高生产卡中，没有狭缝或孔的接收器底座设置在卡的接纳辊下面，并且抽吸装置设置在接纳辊上。 收纳器盖安装在收纳辊的顶部，并在其间限定与抽吸装置连通的密封空间，该抽吸装置控制收纳辊和收纳器之间的所述空间中的空气压力，因此 主要是通过抽吸装置的作用将短纤维从连续的纤维分离出来，所以杂质如垃圾主要从提供的纤维在形成于接收器底层的上游位置的接纳辊下面的自由空间处被除去， 。