公开(公告)号：US20060022340A1

公开(公告)日：2006-02-02

申请号：US10711412

申请日：2004-09-17

申请人： Shu-Lin Ho ,  Pao-Yun Tang

发明人： Shu-Lin Ho ,  Pao-Yun Tang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/013

摘要： An electrical conducting structure including an integrated circuit, a substrate, and a plurality of bumps, wherein at least one bump comprises a first conductive part connected to the integrated circuit at one end; a second conductive part connected to the integrated circuit at one end; a conductive connection part connecting the first conductive part and the second conductive part; a first insulation part surrounding the first conductive part and the second conductive part; and a second insulation part located between the first conductive part and the second conductive part.

摘要翻译： 包括集成电路，基板和多个凸块的导电结构，其中至少一个凸块包括在一端连接到集成电路的第一导电部件; 在一端连接到集成电路的第二导电部件; 连接所述第一导电部和所述第二导电部的导电性连接部; 围绕所述第一导电部和所述第二导电部的第一绝缘部; 以及位于所述第一导电部和所述第二导电部之间的第二绝缘部。

公开(公告)号：US20050270466A1

公开(公告)日：2005-12-08

申请号：US10711617

申请日：2004-09-29

申请人： Pao-Yun Tang ,  Shu-Lin Ho ,  Kei-Hsiung Yang

发明人： Pao-Yun Tang ,  Shu-Lin Ho ,  Kei-Hsiung Yang

IPC分类号： G02F1/1345

CPC分类号： G02F1/1345

摘要： A liquid crystal display module manufactured by a chip-on-glass technology includes at least one glass substrate having a display area and a peripheral area. A plurality of scan and data lines is separately formed on the display area along horizontal and vertical directions. The liquid crystal display module also includes at least one gate driver chip and at least one source driver chip mounted on the peripheral area. The gate and source driver chips transmit signals to the scan and data lines via a plurality of output terminals, and thicknesses of the gate and source driver chips are less than 0.3 mm.

摘要翻译： 通过玻璃技术制造的液晶显示模块包括至少一个具有显示区域和周边区域的玻璃基板。 多个扫描和数据线在水平和垂直方向上分别形成在显示区域上。 液晶显示模块还包括安装在周边区域上的至少一个栅极驱动器芯片和至少一个源极驱动器芯片。 栅极和源极驱动器芯片通过多个输出端子将信号传输到扫描和数据线，并且栅极和源极驱动器芯片的厚度小于0.3mm。

公开(公告)号：US06995474B1

公开(公告)日：2006-02-07

申请号：US10711412

申请日：2004-09-17

申请人： Shu-Lin Ho ,  Pao-Yun Tang

发明人： Shu-Lin Ho ,  Pao-Yun Tang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/013

摘要： An electrical conducting structure including an integrated circuit, a substrate, and a plurality of bumps, wherein at least one bump comprises a first conductive part connected to the integrated circuit at one end; a second conductive part connected to the integrated circuit at one end; a conductive connection part connecting the first conductive part and the second conductive part; a first insulation part surrounding the first conductive part and the second conductive part; and a second insulation part located between the first conductive part and the second conductive part.

摘要翻译： 包括集成电路，基板和多个凸块的导电结构，其中至少一个凸块包括在一端连接到集成电路的第一导电部件; 在一端连接到集成电路的第二导电部件; 连接所述第一导电部和所述第二导电部的导电性连接部; 围绕所述第一导电部和所述第二导电部的第一绝缘部; 以及位于所述第一导电部和所述第二导电部之间的第二绝缘部。

公开(公告)号：US20060175711A1

公开(公告)日：2006-08-10

申请号：US11054693

申请日：2005-02-08

申请人： Pao-Yun Tang ,  Shu-Lin Ho ,  Hsiu-Sheng Hsu ,  Nan-Cheng Huang

发明人： Pao-Yun Tang ,  Shu-Lin Ho ,  Hsiu-Sheng Hsu ,  Nan-Cheng Huang

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/05076 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/90 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for bonding an IC chip to a substrate where the method comprises the steps of providing an IC chip with a plurality of bumps each having a buffer layer and a conductive layer, providing a substrate having a plurality of conductive elements arranged corresponding to the plurality of bumps, placing a non-conductive film between the plurality of conductive devices and their corresponding bumps, and pressing and heating the IC chip and the substrate so that the plurality of bumps are in contact with the plurality of conductive elements respectively. The bonding structure is formed between a first and second substrate where the structure has a buffer layer having an opening and formed on the first substrate, a conductive layer formed on the buffer layer, and a non-conductive film formed between the conductive layer and the second substrate as a bonding medium for the bonding structure.

摘要翻译： 一种用于将IC芯片接合到基板的方法，其中所述方法包括以下步骤：提供具有缓冲层和导电层的多个凸块的IC芯片，提供具有对应于多个布置的多个导电元件的基板 在多个导电器件及其对应的凸块之间放置非导电膜，并且对IC芯片和衬底进行加压和加热，使得多个凸块分别与多个导电元件接触。 接合结构形成在第一和第二基板之间，其中结构具有开口并形成在第一基板上的缓冲层，形成在缓冲层上的导电层，以及形成在导电层和导电层之间的非导电膜 第二基板作为接合结构的接合介质。

公开(公告)号：US08841781B2

公开(公告)日：2014-09-23

申请号：US13253076

申请日：2011-10-05

申请人： Pao-Yun Tang ,  Wei-Hao Sun

发明人： Pao-Yun Tang ,  Wei-Hao Sun

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  G02F1/1345

CPC分类号： H01L21/027 ,  G02F1/13452 ,  H01L24/17 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

摘要翻译： 具有适用于玻璃技术芯片的凸块布局的芯片和驱动IC包括多个第一凸块和用于电连接到显示器的玻璃基板的多个第二凸块。 第一和第二凸起分别设置在芯片的表面和芯片的两个相对的长边附近。 第一凸块的总接触面积与第二凸块的总接触面积的比率在0.8和1.2之间。 因此，可以在整个芯片上均匀地施加施加在用于连接的显示器的芯片和玻璃基板上的压力，从而提高连接的稳定性。

公开(公告)号：US08063497B2

公开(公告)日：2011-11-22

申请号：US12194546

申请日：2008-08-20

申请人： Pao-Yun Tang ,  Wei-Hao Sun

发明人： Pao-Yun Tang ,  Wei-Hao Sun

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/027 ,  G02F1/13452 ,  H01L24/17 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

摘要翻译： 具有适用于玻璃技术芯片的凸块布局的芯片和驱动IC包括多个第一凸块和用于电连接到显示器的玻璃基板的多个第二凸块。 第一和第二凸起分别设置在芯片的表面和芯片的两个相对的长边附近。 第一凸块的总接触面积与第二凸块的总接触面积的比率在0.8和1.2之间。 因此，可以在整个芯片上均匀地施加施加在用于连接的显示器的芯片和玻璃基板上的压力，从而提高连接的稳定性。

公开(公告)号：US07456475B2

公开(公告)日：2008-11-25

申请号：US11553543

申请日：2006-10-27

申请人： Pao-Yun Tang ,  Po-Yang Chen

发明人： Pao-Yun Tang ,  Po-Yang Chen

IPC分类号： H01L27/12

CPC分类号： G02F1/133351 ,  G02F1/13452 ,  G02F2001/136254

摘要： The invention discloses a display panel. A substrate comprising a chip bonding region and a cut cross-section is provided. A first conductive layer is disposed on the chip bonding region. An insulating layer is disposed on the substrate between the first conductive layer and the cut cross-section, covering a sidewall of the first conductive layer. A second conductive layer is disposed on the insulating layer extending until the cut cross-section and electrically connected to the first conductive layer.

摘要翻译： 本发明公开了一种显示面板。 提供了包括芯片接合区域和切割横截面的基板。 第一导电层设置在芯片接合区域上。 绝缘层设置在第一导电层和切割横截面之间的衬底上，覆盖第一导电层的侧壁。 第二导电层设置在绝缘层上，延伸直到切割的横截面并电连接到第一导电层。

公开(公告)号：US20090268147A1

公开(公告)日：2009-10-29

申请号：US12194546

申请日：2008-08-20

申请人： Pao-Yun Tang ,  Wei-Hao Sun

发明人： Pao-Yun Tang ,  Wei-Hao Sun

IPC分类号： G02F1/1345 ,  H01L23/488

CPC分类号： H01L21/027 ,  G02F1/13452 ,  H01L24/17 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

摘要翻译： 具有适用于玻璃技术芯片的凸块布局的芯片和驱动IC包括多个第一凸块和用于电连接到显示器的玻璃基板的多个第二凸块。 第一和第二凸起分别设置在芯片的表面和芯片的两个相对的长边附近。 第一凸块的总接触面积与第二凸块的总接触面积的比率在0.8和1.2之间。 因此，可以在整个芯片上均匀地施加施加在用于连接的显示器的芯片和玻璃基板上的压力，从而提高连接的稳定性。

公开(公告)号：US20090058774A1

公开(公告)日：2009-03-05

申请号：US11930124

申请日：2007-10-31

申请人： Pao-Yun Tang

发明人： Pao-Yun Tang

IPC分类号： G09G3/36

CPC分类号： G02F1/1345 ,  G02F2201/121 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2320/0233 ,  G09G2330/08

摘要： A display apparatus includes a substrate, a daisy chain, a driving circuit, and a conductive portion. The substrate has an electrode line. The daisy chain includes a first conducting wire separated from the electrode line. The first conducting wire has a first terminal and a second terminal. The conductive portion is disposed on the substrate. The first terminal is electrically connected to the electrode line and the second terminal is separated from the driving circuit.

摘要翻译： 显示装置包括基板，菊花链，驱动电路和导电部分。 基板具有电极线。 菊链包括与电极线分离的第一导线。 第一导线具有第一端子和第二端子。 导电部分设置在基板上。 第一端子电连接到电极线，并且第二端子与驱动电路分离。

公开(公告)号：US20080099763A1

公开(公告)日：2008-05-01

申请号：US11553543

申请日：2006-10-27

申请人： Pao-Yun Tang ,  Po-Yang Chen

发明人： Pao-Yun Tang ,  Po-Yang Chen

IPC分类号： H01L29/04 ,  H01L21/00

CPC分类号： G02F1/133351 ,  G02F1/13452 ,  G02F2001/136254

摘要： The invention discloses a display panel. A substrate comprising a chip bonding region and a cut cross-section is provided. A first conductive layer is disposed on the chip bonding region. An insulating layer is disposed on the substrate between the first conductive layer and the cut cross-section, covering a sidewall of the first conductive layer. A second conductive layer is disposed on the insulating layer extending until the cut cross-section and electrically connected to the first conductive layer.

摘要翻译： 本发明公开了一种显示面板。 提供了包括芯片接合区域和切割横截面的基板。 第一导电层设置在芯片接合区域上。 绝缘层设置在第一导电层和切割横截面之间的基板上，覆盖第一导电层的侧壁。 第二导电层设置在绝缘层上，延伸直到切割的横截面并电连接到第一导电层。