公开(公告)号：US20120275215A1

公开(公告)日：2012-11-01

申请号：US13457262

申请日：2012-04-26

申请人： Shuichi TSUKADA ,  Yasuhiro Uchiyama

发明人： Shuichi TSUKADA ,  Yasuhiro Uchiyama

IPC分类号： G11C11/24 ,  H01L27/06

CPC分类号： G11C11/39 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/411 ,  H01L27/075 ,  H01L27/1021 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/7841

摘要： There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

摘要翻译： 提供了包括字线，位线，电源节点，存储元件和电容器的半导体器件。 存储器元件至少包括在位线和电源节点之间形成PN结的第一和第二区域，以及与第二区域形成PN结的第三区域。 电容器包括独立于存储元件的第二区域设置并电连接到存储元件的第二区域的第一电极和连接到字线的第二电极。

公开(公告)号：US20110210302A1

公开(公告)日：2011-09-01

申请号：US13029751

申请日：2011-02-17

申请人： Shuichi TSUKADA ,  Yasuhiro Uchiyama

发明人： Shuichi TSUKADA ,  Yasuhiro Uchiyama

IPC分类号： H01L47/00 ,  H01L27/06

CPC分类号： H01L27/2445 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，嵌入在半导体衬底上形成的沟槽中的第一绝缘膜区域，覆盖第一绝缘膜区域的下表面的栅电极和栅极绝缘膜 设置在栅电极和半导体衬底之间。 半导体器件还包括覆盖第一绝缘膜区域的第一侧面的第一扩散区域和覆盖第一绝缘膜区域的第二侧面的第二扩散区域和覆盖第一绝缘膜区域的上表面的第三扩散区域 第二扩散区。 选择元件包括由栅电极，第一扩散区和第二扩散区构成的场效应晶体管，以及由衬底和第二和第三扩散区构成的双极晶体管。

公开(公告)号：US20100039171A1

公开(公告)日：2010-02-18

申请号：US12606756

申请日：2009-10-27

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G05F1/10

CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/83

摘要： A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.

摘要翻译： 一种电流限制电路，包括：限流元件，用于将输出电流电平限制在限制电流的预定范围内，并且包括具有施加预定电压的源极的第一PMOS晶体管和输出电流为 供应; 以及栅极电压产生电路，用于通过反馈控制产生栅极电压，使得第一PMOS晶体管的预定电压和栅极电压之间的差异与具有与第一PMOS晶体管具有大致相同特性的第二PMOS晶体管的阈值电压重合 第一PMOS晶体管处于预定电流流过第二PMOS晶体管的状态。

公开(公告)号：US20100309716A1

公开(公告)日：2010-12-09

申请号：US12793199

申请日：2010-06-03

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C11/00 ,  G05F1/10 ,  G11C5/14

CPC分类号： G11C13/0069 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0038 ,  H02M3/073 ,  H02M2001/007 ,  H02M2001/009

摘要： A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.

摘要翻译： 电源电压产生电路包括产生第一内部电源电压的第一电荷泵电路和产生第二内部电源电压的第二电荷泵电路。 第二内部电源电压的绝对值大于第一内部电源电压的绝对值。 第一电荷泵电路的输出端子连接到第二电荷泵电路的次级侧充电端子。 次级侧是对应的电荷泵电路的输出侧，充电端子是向相应的电荷泵电路的次级侧输出端子提供辅助电荷的辅助充电端子。 第二电荷泵电路的输出端子输出作为向充电端子施加的第一内部电源电压的值加上规定的电压值的结果的电压值。

公开(公告)号：US20100254184A1

公开(公告)日：2010-10-07

申请号：US12753619

申请日：2010-04-02

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1087 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

摘要： The semiconductor memory device includes a control circuit that performs control of reading data from and writing data into each memory cell. The control circuit includes a flip-flop circuit that stores the data read from the memory cell and stores the data to be written into the memory cell and a dynamic type holding circuit connected to the flip-flop circuit through a switch. The dynamic-type holding circuit temporarily stores the data read from the memory cell. When the data read from the memory cell and then held in the holding circuit is different from the data in the flip-flop circuit to be written, supplied from an outside at a time of writing into the memory cell, control is performed so that the data in the flip-flop circuit is written into the memory cell.

摘要翻译： 半导体存储器件包括控制电路，其执行从每个存储器单元读取数据和将数据写入每个存储器单元的控制。 该控制电路包括一个触发器电路，存储从存储单元读出的数据并存储要写入存储单元的数据和通过开关连接到触发器电路的动态类型保持电路。 动态保持电路临时存储从存储单元读取的数据。 当从存储单元读出然后保持在保持电路中的数据与从写入时从外部提供的要写入的触发器电路中的数据不同时，执行控制，使得 触发器电路中的数据被写入存储单元。

公开(公告)号：US20130033930A1

公开(公告)日：2013-02-07

申请号：US13647626

申请日：2012-10-09

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0038 ,  H02M3/073 ,  H02M2001/007 ,  H02M2001/009

摘要： A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.

公开(公告)号：US20140185373A1

公开(公告)日：2014-07-03

申请号：US14201999

申请日：2014-03-10

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C5/145 ,  G11C13/0004 ,  G11C13/0038 ,  H02M3/073 ,  H02M2001/007 ,  H02M2001/009

摘要： A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.

摘要翻译： 电源电压产生电路包括产生第一内部电源电压的第一电荷泵电路和产生第二内部电源电压的第二电荷泵电路。 第二内部电源电压的绝对值大于第一内部电源电压的绝对值。 第一电荷泵电路的输出端子连接到第二电荷泵电路的次级侧充电端子。 次级侧是对应的电荷泵电路的输出侧，充电端子是向相应的电荷泵电路的次级侧输出端子提供辅助电荷的辅助充电端子。 第二电荷泵电路的输出端子输出作为向充电端子施加的第一内部电源电压的值加上规定的电压值的结果的电压值。

公开(公告)号：US20110080776A1

公开(公告)日：2011-04-07

申请号：US12899106

申请日：2010-10-06

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C5/14 ,  G11C13/0004 ,  G11C2213/15 ,  G11C2213/72

摘要： A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.

摘要翻译： 半导体存储器件包括存储单元，产生第一和第二电压的第一和第二电压产生电路以及控制电路。 包括在存储单元中的存储元件和二极管串联连接在第一和第二线之间。 第一电压没有温度依赖性，第二电压具有与二极管的正向电压相反的温度依赖性。 控制电路在存储单元的读取操作中在第一/第二电压施加第一/第二电压的状态下，根据在存储单元中流动的电流的变化来检测存储元件的电阻状态。

公开(公告)号：US20120314483A1

公开(公告)日：2012-12-13

申请号：US13485722

申请日：2012-05-31

申请人： Shuichi TSUKADA

发明人： Shuichi TSUKADA

IPC分类号： G11C7/06 ,  G11C11/24 ,  G11C7/00

CPC分类号： G11C11/403 ,  G11C11/39 ,  G11C2211/4016

摘要： A semiconductor device includes a bit line, a memory cell, and a control circuit. The memory cell includes a switch circuit coupled to the bit line and a memory element configured to store either one of first and second data. The control circuit controls a voltage of the bit line to turn on the switch element in a first time period and to turn off the switch element in a second time period following the first time period when the control circuit writes the first data to the memory element. The control circuit controls the voltage of the bit line to turn on the switch element in the first time period and to maintain an on-state of the switch circuit in the second time period when the control circuit writes the second data to the memory element.

摘要翻译： 半导体器件包括位线，存储单元和控制电路。 存储单元包括耦合到位线的开关电路和被配置为存储第一和第二数据中的任何一个的存储器元件。 控制电路控制位线的电压以在第一时间段内接通开关元件，并且在控制电路将第一数据写入存储元件的第一时间段之后的第二时间段中关断开关元件 。 控制电路控制位线的电压以在第一时间段内导通开关元件，并且当控制电路将第二数据写入存储元件时，在第二时间段内保持开关电路的接通状态。

公开(公告)号：US20100302888A1

公开(公告)日：2010-12-02

申请号：US12788428

申请日：2010-05-27

申请人： Yuki MORI ,  Kensuke OKONOGI ,  Shuichi TSUKADA

发明人： Yuki MORI ,  Kensuke OKONOGI ,  Shuichi TSUKADA

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/50016

摘要： A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on the side of the gate electrode and, after applying the bias, performing a pause-refresh test for inspecting the data retention capability of the memory cell.

摘要翻译： 通过向栅电极施加偏压来筛选潜在地包括归因于数据保持能力随时间的随机变化的保留故障的存储单元，使得空穴积聚在作为存储单元晶体管的分量的衬底的界面上 栅电极的一侧，并且在施加偏压之后，执行用于检查存储单元的数据保持能力的暂停刷新测试。