公开(公告)号：US10056389B2

公开(公告)日：2018-08-21

申请号：US15011396

申请日：2016-01-29

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/11 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/102 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/74 ,  G11C11/39 ,  H01L29/745 ,  G11C11/41 ,  H01L27/06 ,  H01L27/082 ,  G11C11/411

CPC分类号： H01L27/1104 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/66386 ,  H01L29/732 ,  H01L29/742 ,  H01L29/7455

摘要： A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

公开(公告)号：US09899389B2

公开(公告)日：2018-02-20

申请号：US15426588

申请日：2017-02-07

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/102 ,  H01L21/8249 ,  H01L29/74

CPC分类号： H01L27/1025 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/8229 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

公开(公告)号：US09741413B2

公开(公告)日：2017-08-22

申请号：US15216652

申请日：2016-07-21

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/39 ,  G11C11/418 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/102 ,  H01L27/11 ,  G11C5/14 ,  G11C11/41 ,  G11C11/411 ,  G11C11/416 ,  H01L27/082

CPC分类号： G11C11/00 ,  G11C5/148 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/1104 ,  H01L29/7404

摘要： A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.

公开(公告)号：US09613968B2

公开(公告)日：2017-04-04

申请号：US14590852

申请日：2015-01-06

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/102 ,  H01L27/11 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8229 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/732 ,  H01L29/74 ,  G11C11/39 ,  H01L29/745 ,  G11C11/41 ,  H01L27/06 ,  H01L27/082 ,  G11C11/411

CPC分类号： H01L27/1104 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/66386 ,  H01L29/732 ,  H01L29/742 ,  H01L29/7455

摘要： A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.

公开(公告)号：US20160329094A1

公开(公告)日：2016-11-10

申请号：US15216652

申请日：2016-07-21

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/419 ,  G11C11/39

CPC分类号： G11C11/00 ,  G11C5/148 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/1104 ,  H01L29/7404

摘要： A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.

摘要翻译： 基于用于SRAM集成电路的晶闸管的六晶体管存储单元与操作方法一起被描述。 描述了在降低功耗的同时增加读取这种存储单元的阵列中的选定存储单元的内容的操作速度的方法，以及当存储单元从待机“唤醒”时避免不确定的存储单元状态。

公开(公告)号：US20160189762A1

公开(公告)日：2016-06-30

申请号：US14985259

申请日：2015-12-30

申请人： Simon Peter Tsaoussis

发明人： Simon Peter Tsaoussis

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C7/12 ,  G11C11/39 ,  G11C11/411 ,  G11C2207/12

摘要： A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a first base. The first pull up resistor is connected to the first emitter and the voltage/current input. The second transistor has a second emitter connected to ground, a second collector, and a second base connected to the input/output switch. The second pull up resistor is connected to the first base, the second collector, and the voltage/current input.

公开(公告)号：US08929133B2

公开(公告)日：2015-01-06

申请号：US13691823

申请日：2012-12-02

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Leland Chang ,  Jeffrey W. Sleight

IPC分类号： G11C11/34 ,  H01L21/8232 ,  G11C11/40 ,  H01L27/12

CPC分类号： G11C11/40 ,  G11C11/411 ,  H01L21/8232 ,  H01L27/1203

摘要： A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

摘要翻译： 包括在SOI衬底上制造的SOI衬底和横向双极结型晶体管（BJT）的存储器阵列。 BJT形成第一和第二反相器交叉耦合以形成存储单元。 读出电路输出存储单元的二进制状态。 电源被配置为向读取电路提供Vdd电压，并将Vcc和Vee电压提供给第一组横向双极晶体管和第二组横向双极晶体管，其中Vee电压至少为零伏， Vcc电压大于Vee电压并且等于或小于Vdd电压。

公开(公告)号：US08737124B2

公开(公告)日：2014-05-27

申请号：US13457262

申请日：2012-04-26

申请人： Shuichi Tsukada ,  Yasuhiro Uchiyama

发明人： Shuichi Tsukada ,  Yasuhiro Uchiyama

IPC分类号： G11C11/24 ,  H01L27/06 ,  H01L27/102 ,  G11C11/39 ,  H01L49/02 ,  H01L29/78

CPC分类号： G11C11/39 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/411 ,  H01L27/075 ,  H01L27/1021 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/7841

摘要： There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

摘要翻译： 提供了包括字线，位线，电源节点，存储元件和电容器的半导体器件。 存储器元件至少包括在位线和电源节点之间形成PN结的第一和第二区域，以及与第二区域形成PN结的第三区域。 电容器包括独立于存储元件的第二区域设置并电连接到存储元件的第二区域的第一电极和连接到字线的第二电极。

公开(公告)号：US6128216A

公开(公告)日：2000-10-03

申请号：US76766

申请日：1998-05-13

申请人： Wendell P. Noble, Jr. ,  Leonard Forbes

发明人： Wendell P. Noble, Jr. ,  Leonard Forbes

IPC分类号： G11C11/39 ,  G11C11/411 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00 ,  G11C11/36

CPC分类号： H01L27/11 ,  G11C11/39 ,  G11C11/411

摘要： Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

摘要翻译： 区域有效的静态存储单元和包含p-n-p-n或n-p-n-p晶体管的阵列，其可以在双稳态导通状态下被锁存。 每个晶体管存储单元包括在写操作期间脉冲偏置以锁存单元的门。 还提供了其中晶体管共享公共区域的链接存储器单元。

公开(公告)号：US3725881A

公开(公告)日：1973-04-03

申请号：US3725881D

申请日：1971-08-25

申请人： INTERSIL INC

发明人： DELLOR R

IPC分类号： G11C11/411 ,  H01L27/10 ,  G11C11/40 ,  H03K3/286

CPC分类号： G11C11/411 ,  H01L27/10

摘要： A pair of transistors are interconnected with a single resistor as a bipolar integrated circuit to provide a structure having two stable states which may then represent binary states in a memory unit. Isolation and interconnection requirements are minimized to thus materially increase the packing density possible in a single chip.

摘要翻译： 一对晶体管与作为双极集成电路的单个电阻器互连，以提供具有两个稳定状态的结构，然后可以在存储器单元中表示二进制状态。 隔离和互连要求最小化，从而在单个芯片中实质上增加了封装密度。