公开(公告)号：US20080208939A1

公开(公告)日：2008-08-28

申请号：US12071903

申请日：2008-02-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

IPC分类号： G06F5/01 ,  G06F7/483 ,  G06F17/00

CPC分类号： H03M13/2957 ,  H03M13/3905 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588

摘要： A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized.

摘要翻译： 一种解码器，具有生成用于输入数据的外部信息的元素解码单元，包括指数位置确定单元，当从元素解码单元输出的外部信息被输入时，从外部信息中排除符号位以外的信息，指定指数为 一个位号，其中与符号位不同的值首先出现，一个尾数获得单元获取位于该指数旁边位置的1位或多个位的信息作为外部信息中的尾数，存储单元存储 指数和尾数，以及恢复单元，通过读取存储在存储单元中的指数和尾数来恢复外部信息，其中元素解码单元基于恢复的外部信息进行迭代解码。

公开(公告)号：US20080141103A1

公开(公告)日：2008-06-12

申请号：US12068707

申请日：2008-02-11

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6306 ,  H03M13/635 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1812

摘要： Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

摘要翻译： 公开了一种发送装置，其发送通过将奇偶校验位加到信息比特而获得的系统代码。 当在未插入虚拟位的情况下，系统代码的码率是由解码特性确定的特定范围内的值时，伪位插入部分将伪位插入信息位并移位解码特性，使得 码率假定在移位之后由解码特性确定的特定范围之外的值。 编码部分对虚拟位被插入的信息比特进行系统编码，并且从编码结果中删除伪比特以产生系统代码，并且速率匹配部分执行速率匹配， 系统码等于由物理信道传输速率确定的大小，并传输系统码。

公开(公告)号：US08250446B2

公开(公告)日：2012-08-21

申请号：US12071903

申请日：2008-02-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

IPC分类号： G06F11/00

CPC分类号： H03M13/2957 ,  H03M13/3905 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588

摘要： A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized.

摘要翻译： 一种解码器，具有生成用于输入数据的外部信息的元素解码单元，包括指数位置确定单元，当从元素解码单元输出的外部信息被输入时，从外部信息中排除符号位以外的信息，指定指数为 一个位号，其中与符号位不同的值首先出现，一个尾数获得单元获取位于该指数旁边位置的1位或多个位的信息作为外部信息中的尾数，存储单元存储 指数和尾数，以及恢复单元，通过读取存储在存储单元中的指数和尾数来恢复外部信息，其中元素解码单元基于恢复的外部信息进行迭代解码。

公开(公告)号：US08028223B2

公开(公告)日：2011-09-27

申请号：US12068707

申请日：2008-02-11

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6306 ,  H03M13/635 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1812

摘要： Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

摘要翻译： 公开了一种发送装置，其发送通过将奇偶校验位加到信息比特而获得的系统代码。 当在未插入虚拟位的情况下，系统代码的码率是由解码特性确定的特定范围内的值时，伪位插入部分将伪位插入信息位并移位解码特性，使得 码率假定在移位之后由解码特性确定的特定范围之外的值。 编码部分对虚拟位被插入的信息比特进行系统编码，并且从编码结果中删除伪比特以产生系统代码，并且速率匹配部分执行速率匹配， 系统码等于由物理信道传输速率确定的大小，并传输系统码。

公开(公告)号：US08780792B2

公开(公告)日：2014-07-15

申请号：US11156894

申请日：2005-06-21

申请人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki

发明人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki

IPC分类号： H04W4/00

CPC分类号： H04L1/0075 ,  H04L1/0003 ,  H04L1/0026 ,  H04L1/0066 ,  H04L1/1671 ,  H04L1/1812 ,  H04W36/0055 ,  H04W36/02 ,  H04W88/02 ,  H04W92/10

摘要： An mobile station implements data transport which allows for handover. The mobile station transmits a second datum in response to a first datum received from a wireless base station, the mobile station being characterized in that it comprises: a detection unit which detects that handover is to be performed; and a control unit which provides control such that, in cases where the detection has been made, the changeover timing of the transmission destination for the second datum is made later than the changeover timing of the reception channel for the first datum.

摘要翻译： 移动台实现允许切换的数据传输。 移动台响应于从无线基站接收到的第一数据发送第二数据，其特征在于它包括：检测单元，检测是否执行切换; 以及控制单元，其提供控制，使得在进行检测的情况下，将第二数据的发送目的地的切换定时晚于第一数据的接收信道的切换定时。

公开(公告)号：US08700979B2

公开(公告)日：2014-04-15

申请号：US13529390

申请日：2012-06-21

申请人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

发明人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

IPC分类号： H03M13/03

CPC分类号： H04L1/0057 ,  H03M13/2981 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H03M13/6591 ,  H04L1/005 ,  H04L1/0071

摘要： An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.

摘要翻译： 纠错码解码装置包括：第一解码电路，字长缩小电路，被配置为减少与由第一解码电路执行的解码处理之后获得的多个比特相对应的第一外部值的比特长度，第一预定次数 并且减少字串中包含的字的位长度;以及第二解码电路，被配置为通过执行解码处理来对位串进行解码，第二预定次数用于计算第二外部值和包含在位串中的位的后验值 根据包含具有缩减比特长度的字的字串，使用具有缩小比特长度的第一外部值作为第二先验概率，其中多个比特之间的相应比特是预定值。

公开(公告)号：US08443253B2

公开(公告)日：2013-05-14

申请号：US12876541

申请日：2010-09-07

申请人： Kazuaki Imafuku ,  Kazuhisa Obuchi ,  Shunji Miyazaki ,  Hideaki Yamada ,  Mutsumi Saito ,  Masaru Inoue ,  Shingo Hotta

发明人： Kazuaki Imafuku ,  Kazuhisa Obuchi ,  Shunji Miyazaki ,  Hideaki Yamada ,  Mutsumi Saito ,  Masaru Inoue ,  Shingo Hotta

IPC分类号： H03M13/27 ,  H03M13/29

CPC分类号： H03M13/2957 ,  H03M13/276 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/6566

摘要： A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit selects by which of the first bank configuration and the second bank configuration the memory unit functions in accordance with a communication method of a coded signal and accesses the memory unit in accordance with the selected bank configuration.

摘要翻译： turbo解码装置包括存储单元，该存储单元将数据存储在对以turbo码编码的编码信号进行解码的处理中执行的交织处理以及访问存储器单元以读取和写入数据的存取单元。 存储器单元包括存储器电路，并通过耦合存储器电路而形成为一个存储器空间。 此外，存储电路用作第一存储体配置，通过该第一存储体配置，根据存储器电路的组合，将第一容量分配给每个存储体或第二存储体配置，通过该配置将第二容量分配给每个存储体。 此外，访问单元根据编码信号的通信方法选择第一存储体配置和第二存储体配置中的哪一个，存储单元根据所选择的存储体配置访问存储单元。

公开(公告)号：US08234557B2

公开(公告)日：2012-07-31

申请号：US13345969

申请日：2012-01-09

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/2903 ,  H03M13/635 ,  H03M13/653

摘要： A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.

摘要翻译： 发送通信系统中的发送装置，其中通过系统编码获得的系统代码，其中通过对其中插入有虚拟位的信息比特和通过从系统编码的结果中删除虚拟比特来发送。 传输设备基于turbo编码器中的交织部分的交织模式将伪比特插入到信息比特中; 执行插入虚拟位的信息位的系统编码，然后从系统编码的结果中删除虚拟位以产生系统代码; 并发送系统代码。 通过考虑交织模式，预先确定在交织之后存在于开始和结束的规定数量的范围内的原始位位置，并且虚拟位插入部分执行控制以便不插入 虚拟位进入原始位位置。

公开(公告)号：US08213535B2

公开(公告)日：2012-07-03

申请号：US12948341

申请日：2010-11-17

申请人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

发明人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

IPC分类号： H04L27/00

CPC分类号： H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

摘要： A method of transmitting data by transmitting apparatus, that includes controlling generation of bit sequences to adjust an occupation rate of systematic bits in a first data block including systematic bits and parity bits, which is obtained by encoding first data in a first encoding process, and is equal or closer to an occupation rate of systematic bits in a second data block including systematic bits and parity bits, which is obtained by encoding second data in a second encoding process, and to adjust an occupation rate of parity bits in the first data block that is closer to an occupation rate of parity bits in the second data block, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks and performs multi-level modulation for transmission based on the generated bit sequences.

摘要翻译： 一种发送装置发送数据的方法，包括控制比特序列的产生，以调整包含系统比特和奇偶校验比特在内的第一数据块中的系统比特的占有率，该第一数据块是通过在第一编码处理中对第一数据进行编码而获得的，以及 在第二数据块中的系统比特的占有率等于或更接近于包括通过在第二编码处理中对第二数据进行编码而获得的系统比特和奇偶校验比特的第二数据块的占有率，并且调整第一数据块中的奇偶校验比特的占有率 关于使用包括在第一和第二数据块中的位产生的比特序列的第一比特位置，更靠近第二数据块中的奇偶校验位的占有率，并且基于生成的比特执行用于发送的多级调制 序列。

公开(公告)号：US07685504B2

公开(公告)日：2010-03-23

申请号：US10963811

申请日：2004-10-14

申请人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki

发明人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki

IPC分类号： H03M13/03

CPC分类号： H04L1/0068 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1819 ,  H04L1/1845

摘要： A method and apparatus operable to execute an error correction decoding process, while controlling the increase in the amount of data that is stored in the receiving apparatus, is disclosed. Data is preferably transmitted to a receiving apparatus to execute the error correction decoding process using received data and re-transmitted data. Transmitting data is generated by executing the rate matching process to a first part of the error correction coded data and generating a second transmitting data. The second transmitting data includes at least the data not included in the first part by executing the rate matching process. Also included is a transmitting means for executing the transmission of the second transmitting data as the re-transmission after the transmission of the first transmitting data.

摘要翻译： 公开了一种在控制存储在接收装置中的数据量的增加的同时执行纠错解码处理的方法和装置。 优选地，将数据发送到接收装置，以使用接收的数据和重新发送的数据来执行纠错解码处理。 通过对纠错编码数据的第一部分执行速率匹配处理并产生第二发送数据来生成发送数据。 第二发送数据至少包括通过执行速率匹配处理而不包括在第一部分中的数据。 还包括发送装置，用于在发送第一发送数据之后执行第二发送数据的发送作为再发送。