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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20110062432A1

    公开(公告)日：2011-03-17

    申请号：US12879635

    申请日：2010-09-10

    申请人： Shunpei Yamazaki ,  Masayuki Sakakura ,  Jun Koyama ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Masami Jintyou ,  Kenichi Okazaki

    发明人： Shunpei Yamazaki ,  Masayuki Sakakura ,  Jun Koyama ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Masami Jintyou ,  Kenichi Okazaki

    IPC分类号： H01L29/786 ,  H01L21/44

    CPC分类号： H01L29/7869 ,  H01L27/1225

    摘要： An object is to realize low power consumption while manufacturing a semiconductor device including a thin film transistor whose parasitic capacitance is reduced. Part of an insulating layer covering the periphery of a gate electrode layer is formed to be thick. Specifically, a stack including a spacer insulating layer and a gate insulating layer is formed. The thick part of the insulating layer covering the periphery of the gate electrode layer reduces parasitic capacitance formed between the gate electrode layer of the thin film transistor and another electrode layer (another wiring layer) overlapping with the gate electrode layer.

    摘要翻译： 目的是在制造包括其寄生电容减小的薄膜晶体管的半导体器件的同时实现低功耗。 覆盖栅电极层周围的绝缘层的一部分形成为较厚。 具体地，形成包括间隔绝缘层和栅极绝缘层的堆叠。 覆盖栅电极层周围的绝缘层的厚部减小了在薄膜晶体管的栅电极层与与栅电极层重叠的另一电极层（另一布线层）之间形成的寄生电容。

    Logic circuit, light emitting device, semiconductor device, and electronic device
    9.
    发明授权
    Logic circuit, light emitting device, semiconductor device, and electronic device 有权
    逻辑电路，发光器件，半导体器件和电子器件

    公开(公告)号：US08305109B2

    公开(公告)日：2012-11-06

    申请号：US12880312

    申请日：2010-09-13

    申请人： Kenichi Okazaki ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Shunpei Yamazaki

    发明人： Kenichi Okazaki ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Shunpei Yamazaki

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H01L27/1233 ,  H01L27/0207 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288

    摘要： An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved.

    摘要翻译： 目的是获得使用氧化物半导体的薄膜晶体管的期望阈值电压。 另一个目的是抑制阈值电压随时间的变化。 具体地，目的是将薄膜晶体管施加到使用具有期望阈值电压的晶体管形成的逻辑电路。 为了实现上述目的，可以在相同的衬底上形成包括具有不同厚度的氧化物半导体层的薄膜晶体管，并且其阈值电压由氧化物半导体层的厚度控制的薄膜晶体管可以用于形成 逻辑电路。 此外，通过使用与脱水或脱氢处理之后形成的氧化物绝缘膜接触的氧化物半导体膜，抑制了阈值电压随时间的变化，并且可以提高逻辑电路的可靠性。