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    SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
    1.
    发明申请
    SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION 有权
    具有跨点数据写入操作的单端SRAM

    公开(公告)号：US20130194861A1

    公开(公告)日：2013-08-01

    申请号：US13562330

    申请日：2012-07-31

    申请人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    发明人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

    摘要翻译： 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

    Single-ended SRAM with cross-point data-aware write operation
    2.
    发明授权
    Single-ended SRAM with cross-point data-aware write operation 有权
    具有跨点数据感知写操作的单端SRAM

    公开(公告)号：US08693237B2

    公开(公告)日：2014-04-08

    申请号：US13562330

    申请日：2012-07-31

    申请人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    发明人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

    摘要翻译： 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

    SRAM writing system and related apparatus
    4.
    发明授权
    SRAM writing system and related apparatus 有权
    SRAM写入系统及相关设备

    公开(公告)号：US08325512B2

    公开(公告)日：2012-12-04

    申请号：US13070977

    申请日：2011-03-24

    申请人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    发明人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

    摘要翻译： 提供了SRAM写入系统和相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

    SRAM WRITING SYSTEM AND RELATED APPARATUS
    6.
    发明申请
    SRAM WRITING SYSTEM AND RELATED APPARATUS 有权
    SRAM写入系统及相关设备

    公开(公告)号：US20110235444A1

    公开(公告)日：2011-09-29

    申请号：US13070977

    申请日：2011-03-24

    申请人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    发明人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413

    摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

    摘要翻译： 提供SRAM写入系统及相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
    8.
    发明申请
    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL 有权
    无干扰的静态随机存取存储器单元

    公开(公告)号：US20110128796A1

    公开(公告)日：2011-06-02

    申请号：US12772238

    申请日：2010-05-03

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C11/412

    摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

    摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

    STATIC MEMORY CELL
    9.
    发明申请
    STATIC MEMORY CELL 有权
    静态存储单元

    公开(公告)号：US20150162077A1

    公开(公告)日：2015-06-11

    申请号：US14200040

    申请日：2014-03-07

    申请人： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

    发明人： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

    IPC分类号： G11C11/412 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C11/413

    摘要： A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

    摘要翻译： 提供静态存储单元。 静态存储单元包括数据锁存电路和电压提供器。 数据锁存电路被配置为存储位数据。 数据锁存电路具有第一反相器和第二反相器，并且第一反相器和第二反相器彼此耦合。 第一反相器和第二反相器分别接收第一电压和第二电压作为电源电压。 电压提供器向数据锁存电路提供第一电压和第二电压。 当位数据被写入数据锁存电路时，电压提供器根据位数据调节第一和第二电压之一的电压值。