公开(公告)号：US06665215B2

公开(公告)日：2003-12-16

申请号：US10117448

申请日：2002-04-05

申请人： Sigrid Thomas ,  Leïla Aitouarab

发明人： Sigrid Thomas ,  Leïla Aitouarab

IPC分类号： G11C1604

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/26

摘要： In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.

摘要翻译： 在用于读取存储器单元的装置中，预充电电路连接到要读取的存储器单元和与要读取的存储器单元相关联的参考单元。 预充电电路将差分放大器的输出预充电到预定的电压电平。 读取装置还包括连接到差分放大器的输出的具有高阈值和低阈值的反相器。 预定的电压电平对应于高和低阈值之间的中间电平。

公开(公告)号：US06798680B2

公开(公告)日：2004-09-28

申请号：US10172179

申请日：2002-06-14

申请人： Sigrid Thomas

发明人： Sigrid Thomas

IPC分类号： G11C506

CPC分类号： H01L27/11233 ,  G11C17/12 ,  H01L27/112

摘要： A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.

摘要翻译： 由单元形成的只读存储器，每个单元在选择线和位线之间包括存储元件和选择MOS晶体管的串联连接，栅极连接到读控制线。 空白单元的存储元件是P沟道MOS晶体管，并且编程单元的存储元件是均匀的N型掺杂半导体区域。

公开(公告)号：US20120199867A1

公开(公告)日：2012-08-09

申请号：US13266975

申请日：2010-04-29

申请人： Sigrid Thomas ,  Victor Thomas

发明人： Sigrid Thomas ,  Victor Thomas

IPC分类号： H01L33/62 ,  H01L21/50

CPC分类号： G06K19/07749 ,  G06K19/0776 ,  H01L21/6835 ,  H01L23/66 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic component is attached to a product, using a transfer method involving the use of a transfer sheet including a substrate sheet and at least one transfer layer covering a portion of the front surface of the substrate sheet. The transfer method consists in: placing the transfer layer in contact with the product; applying a pressure against the back surface of the substrate sheet; and finally removing the substrate sheet, said at least one transfer layer remaining affixed to the product. In addition, the attachment method includes a step prior to the transfer method, during which at least one electronic assembly including at least one electronic chip attached to at least one wire is positioned between the product and the substrate sheet, such that at least one portion of each assembly is held in place by a transfer layer following the removal of the substrate sheet.

摘要翻译： 使用包括使用包括基片的转印片和覆盖基片的前表面的一部分的至少一个转印层的转印方法将电子元件附着到产品上。 转印方法在于：将转印层放置在与产品接触的位置; 对基片的背面施加压力; 最后移除基片，所述至少一个转印层保留在产品上。 此外，附接方法包括在传送方法之前的步骤，在此期间，至少一个电子组件包括附接到至少一根线的至少一个电子芯片，位于产品和基片之间，使得至少一个部分 每个组件在移除基片之后通过转移层保持在适当的位置。

公开(公告)号：US06775175B2

公开(公告)日：2004-08-10

申请号：US10233052

申请日：2002-08-30

申请人： Sigrid Thomas

发明人： Sigrid Thomas

IPC分类号： G11C1124

CPC分类号： G11C17/18

摘要： A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

摘要翻译： 存储器件包括以矩阵形式排列的多个存储单元。 每个存储单元包括串联连接的晶体管和电容器。 每个存储单元链接到连接列的存储单元的位线。 每个存储单元也链接到字线和第三行。 存储器单元的晶体管的栅极连接到字线，每个字线被连接到相应列中的晶体管的栅极。 第三条线连接到一行存储器单元的晶体管的源极。 位线连接到列的晶体管的电容器。 因此，可以通过字列和第三行来控制晶体管的栅极和源极之间的电压。

公开(公告)号：US06639838B2

公开(公告)日：2003-10-28

申请号：US10139621

申请日：2002-05-06

申请人： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

发明人： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

IPC分类号： G11C1606

CPC分类号： G11C16/0416

摘要： A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

摘要翻译： 具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。 该选择晶体管用于由存储器单元的源选择单词。 以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。 独立于该选择，高电压切换到存储器单元的栅极和漏极。 这使得能够减少所需数量的高压开关。

公开(公告)号：US06639427B2

公开(公告)日：2003-10-28

申请号：US09996071

申请日：2001-11-28

申请人： Cyrille Dray ,  Sigrid Thomas

发明人： Cyrille Dray ,  Sigrid Thomas

IPC分类号： H03K190185

CPC分类号： H03K19/00315 ,  G11C5/145 ,  G11C8/08 ,  G11C16/0441 ,  G11C16/30

摘要： A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

公开(公告)号：US09171248B2

公开(公告)日：2015-10-27

申请号：US13991872

申请日：2011-11-29

申请人： Rodolphe Heliot ,  Marc Belleville ,  Sigrid Thomas

发明人： Rodolphe Heliot ,  Marc Belleville ,  Sigrid Thomas

IPC分类号： G06F15/18 ,  G06N3/04 ,  G06N3/063

CPC分类号： G06N3/04 ,  G06N3/063

摘要： Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network.

摘要翻译： 神经元电路是被配置为模仿生物神经网络的行为的多细胞网络。 提供神经形态电路，其包括每个由网络中的神经元地址识别的神经元网络，每个神经元能够接收和处理至少一个输入信号，然后在神经元的输出上发射表示事件的信号， 发生在神经元内部，以及可编程存储器，其由每个与相应神经元相关联的基本存储器组成。 作为突触后地址和权重的存储器的基本存储器包括由导体链接到相关神经元的输出的激活输入，以直接接收由该神经元发射的事件信号而不通过地址编码器或解码器。 从由神经元激活的基本记忆提取的突触前地址以相关的突触权重作为神经网络的输入。

公开(公告)号：US20130262358A1

公开(公告)日：2013-10-03

申请号：US13991872

申请日：2011-11-29

申请人： Rodolphe Heliot ,  Marc Belleville ,  Sigrid Thomas

发明人： Rodolphe Heliot ,  Marc Belleville ,  Sigrid Thomas

IPC分类号： G06N3/04

CPC分类号： G06N3/04 ,  G06N3/063

摘要： Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network.

摘要翻译： 神经元电路是被配置为模仿生物神经网络的行为的多细胞网络。 提供神经形态电路，其包括每个由网络中的神经元地址识别的神经元网络，每个神经元能够接收和处理至少一个输入信号，然后在神经元的输出上发出一个表示事件的信号， 发生在神经元内部，以及可编程存储器，其由每个与相应神经元相关联的基本存储器组成。 作为突触后地址和权重的存储器的基本存储器包括由导体链接到相关神经元的输出的激活输入，以直接接收由该神经元发射的事件信号而不通过地址编码器或解码器。 从由神经元激活的基本记忆提取的突触前地址以相关的突触权重作为神经网络的输入。