公开(公告)号：US20020090758A1

公开(公告)日：2002-07-11

申请号：US09956486

申请日：2001-09-18

Applicant: Silicon Genesis Corporation

Inventor： Francois J. Henley ,  Nathan Cheung

IPC: H01L021/44

CPC classification number: H01L21/26506 ,  H01L21/26593 ,  H01L21/76254 ,  H01L21/84 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

Abstract: A process for forming an integrated circuit device structure. The process includes forming a first gate layer on a thickness of material on a donor substrate. The donor substrate has a cleave region underlying the gate layer. The process also includes joining the donor substrate to a handle substrate where the gate layer face the handle substrate; and separating the thickness of material at the cleave region from the donor substrate to define a handle substrate comprising the gate layer and an overlying thickness of material. The process forms a plurality of second gate structures on the thickness of material, where at least one of the first gate structures facing one of the second gate structures forming a channel region therebetween.

Abstract translation: 一种用于形成集成电路器件结构的工艺。 该工艺包括在施主衬底上形成材料厚度上的第一栅极层。 施主衬底具有在栅极层下面的解理区域。 该方法还包括将施主衬底接合到处理衬底，其中栅极层面对手柄衬底; 以及将所述切割区域处的材料的厚度从所述施主衬底分离以限定包括所述栅极层和覆盖材料厚度的手柄衬底。 该过程在材料的厚度上形成多个第二栅极结构，其中第一栅极结构中的至少一个面对第二栅极结构中的一个在其间形成沟道区。

公开(公告)号：US20020055266A1

公开(公告)日：2002-05-09

申请号：US10017044

申请日：2001-12-13

Applicant: Silicon Genesis Corporation

Inventor： Francois J. Henley ,  Nathan Cheung

IPC: H01L021/301 ,  H01L021/46 ,  H01L021/78 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01L21/187 ,  B81C1/0038 ,  B81C2201/0191 ,  B81C2201/0192 ,  H01L21/2007 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/304 ,  H01L21/7624 ,  H01L21/76254 ,  H01L21/7813 ,  Y10S117/915 ,  Y10S156/93 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T156/19 ,  Y10T428/21 ,  Y10T428/24893 ,  Y10T428/249956

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract translation: 一种用于从供体衬底（10）形成材料（12）的膜的技术。 该技术具有以选择的方式将能量粒子（22）通过施主衬底（10）的表面引入到表面下方的选定深度（20）的步骤，其中颗粒具有相对高的浓度以限定施主衬底 所选深度以上的材料（12）和所选深度处的图案的颗粒。 诸如加压流体的能量源被引导到供体基底的选定区域，以在所选择的深度（20）处引发基底（10）的受控切割作用，因此所述切割动作提供扩张切割前缘以释放供体 来自供体衬底的剩余部分的材料。

公开(公告)号：US20040097055A1

公开(公告)日：2004-05-20

申请号：US10402356

申请日：2003-03-26

Applicant: Silicon Genesis Corporation

Inventor： Francois J. Henley ,  Nathan Cheung

IPC: H01L021/322

CPC classification number: H01L21/3223 ,  H01L21/2007 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/3226 ,  H01L21/76254

Abstract: A technique for forming a gettering layer in a wafer made using a controlled cleaving process. The gettering layer can be made by implanting using beam line or plasma immersion ion implantaion, or made by forming a film of material such as polysilicon by way of chemical vapor deposition. A controlled cleaving process is used to form the wafer, which is a multilayered silicon on insulator substrate. The gettering layer removes and/or attracts impurities in the wafer, which can be detrimental to the functionality and reliability of an integrated circuit device made on the wafer.

Abstract translation: 一种在使用受控断裂工艺制成的晶片中形成吸气层的技术。 吸气层可以通过使用束线或等离子体浸没离子注入植入，或者通过通过化学气相沉积形成诸如多晶硅的材料的膜制成。 使用受控的裂解工艺来形成绝缘体上多层硅衬底的晶片。 吸杂层去除和/或吸引晶片中的杂质，这可能不利于在晶片上制成的集成电路器件的功能和可靠性。