公开(公告)号：US10679914B2

公开(公告)日：2020-06-09

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/16 ,  H01L21/78 ,  H01L21/56

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20180254232A1

公开(公告)日：2018-09-06

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US10201086B2

公开(公告)日：2019-02-05

申请号：US15295010

申请日：2016-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Cheng-Hsiang Liu ,  Chang-Lun Lu ,  Jun-Cheng Liao ,  Cheng-Yi Chen

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/34

Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.

公开(公告)号：US20180042112A1

公开(公告)日：2018-02-08

申请号：US15295010

申请日：2016-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Cheng-Hsiang Liu ,  Chang-Lun Lu ,  Jun-Cheng Liao ,  Cheng-Yi Chen

IPC: H05K1/18 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/111 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/09663 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.

公开(公告)号：US11081415B2

公开(公告)日：2021-08-03

申请号：US16862024

申请日：2020-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/16

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20200258802A1

公开(公告)日：2020-08-13

申请号：US16862024

申请日：2020-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/16

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.