公开(公告)号：US20170243834A1

公开(公告)日：2017-08-24

申请号：US15149576

申请日：2016-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Mao-Hua Yeh ,  Hung-Yuan Li ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

公开(公告)号：US20190043798A1

公开(公告)日：2019-02-07

申请号：US16157430

申请日：2018-10-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Hung-Yuan Li ,  Chieh-Lung Lai ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US20160163632A1

公开(公告)日：2016-06-09

申请号：US14817238

申请日：2015-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsien-Wen Chen ,  Shih-Ching Chen ,  Chieh-Lung Lai

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/81 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure.

Abstract translation: 封装结构包括具有相对的第一和第二表面的电介质层，形成在第一表面上并具有穿过电介质层的多个导电通孔的布线层，设置在电介质层的第一表面上并电连接的电子部件 布线层，封装电子部件的密封剂和设置在第二表面上并与导电通孔电连接的封装基板。 通过将电介质层替换为常规硅板，并且布线层作为电子部件和封装基板之间的信号传输介质，封装结构不需要通过硅通孔。 因此，封装结构具有简单的制造工艺和低制造成本。 本发明还提供一种制造封装结构的方法。

公开(公告)号：US20150325556A1

公开(公告)日：2015-11-12

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。

公开(公告)号：US10679914B2

公开(公告)日：2020-06-09

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/16 ,  H01L21/78 ,  H01L21/56

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20180254232A1

公开(公告)日：2018-09-06

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US09831191B2

公开(公告)日：2017-11-28

申请号：US15149576

申请日：2016-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Mao-Hua Yeh ,  Hung-Yuan Li ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

公开(公告)号：US09515039B2

公开(公告)日：2016-12-06

申请号：US14983738

申请日：2015-12-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Lu-Yi Chen ,  Yu-Chuan Chen ,  Chang-Lun Lu

IPC: H05K1/00 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05567 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Abstract translation: 提供了一种衬底结构，其包括具有多个导电焊盘的衬底本体，以及设置在导电焊盘上的多个第一导电凸块和多个第二导电凸块。 每个第二导电凸块的宽度小于每个第一导电凸块，并且相对于基板主体的高度大于每个第一导电凸块相对于基板主体的高度。 因此，可以补偿回流处理后的第一预焊锡层和第二预焊锡层之间的高度差，因此第一导电凸块和第二导电凸块具有均匀的高度。

公开(公告)号：US09899309B2

公开(公告)日：2018-02-20

申请号：US15084762

申请日：2016-03-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Ching Chen ,  Shih-Liang Peng ,  Chieh-Lung Lai ,  Jia-Wei Pan ,  Chang-Lun Lu

IPC: H01L23/00 ,  H01L23/48 ,  H01L29/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L21/4846 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/15151

Abstract: A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided.

公开(公告)号：US09502335B2

公开(公告)日：2016-11-22

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/49 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。