公开(公告)号：US10461002B2

公开(公告)日：2019-10-29

申请号：US15646695

申请日：2017-07-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu ,  Shih-Ching Chen

IPC: H05K13/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.

公开(公告)号：US10141233B2

公开(公告)日：2018-11-27

申请号：US15008097

申请日：2016-01-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L23/34 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31

Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09899309B2

公开(公告)日：2018-02-20

申请号：US15084762

申请日：2016-03-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Ching Chen ,  Shih-Liang Peng ,  Chieh-Lung Lai ,  Jia-Wei Pan ,  Chang-Lun Lu

IPC: H01L23/00 ,  H01L23/48 ,  H01L29/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L21/4846 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/15151

Abstract: A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided.

公开(公告)号：US20170084562A1

公开(公告)日：2017-03-23

申请号：US15366543

申请日：2016-12-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jyun-Ling Tsai ,  Chang-Lun Lu

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2224/81359 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.

公开(公告)号：US20160322323A1

公开(公告)日：2016-11-03

申请号：US14983738

申请日：2015-12-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Lu-Yi Chen ,  Yu-Chuan Chen ,  Chang-Lun Lu

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05567 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Abstract translation: 提供了一种衬底结构，其包括具有多个导电焊盘的衬底本体，以及设置在导电焊盘上的多个第一导电凸块和多个第二导电凸块。 每个第二导电凸块的宽度小于每个第一导电凸块，并且相对于基板主体的高度大于每个第一导电凸块相对于基板主体的高度。 因此，可以补偿回流处理后的第一预焊锡层和第二预焊锡层之间的高度差，因此第一导电凸块和第二导电凸块具有均匀的高度。

公开(公告)号：US20190057911A1

公开(公告)日：2019-02-21

申请号：US16166811

申请日：2018-10-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00

Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09831191B2

公开(公告)日：2017-11-28

申请号：US15149576

申请日：2016-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Mao-Hua Yeh ,  Hung-Yuan Li ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

公开(公告)号：US09515039B2

公开(公告)日：2016-12-06

申请号：US14983738

申请日：2015-12-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Lu-Yi Chen ,  Yu-Chuan Chen ,  Chang-Lun Lu

IPC: H05K1/00 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05567 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Abstract translation: 提供了一种衬底结构，其包括具有多个导电焊盘的衬底本体，以及设置在导电焊盘上的多个第一导电凸块和多个第二导电凸块。 每个第二导电凸块的宽度小于每个第一导电凸块，并且相对于基板主体的高度大于每个第一导电凸块相对于基板主体的高度。 因此，可以补偿回流处理后的第一预焊锡层和第二预焊锡层之间的高度差，因此第一导电凸块和第二导电凸块具有均匀的高度。

公开(公告)号：US09263380B2

公开(公告)日：2016-02-16

申请号：US14515970

申请日：2014-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jyun-Ling Tsai ,  Chang-Lun Lu

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer.

Abstract translation: 提供了一种半导体插入器，其包括：具有限定有内部区域的表面和围绕内部区域的周边区域的基板; 多个导电柱，其嵌入到所述基板主体中，并且每个具有从所述基板主体的表面露出的一端; 形成在所述基板主体的表面上并且具有形成在所述周边区域中的周边部分的钝化层，形成在所述内部区域中的所述导电柱的暴露端的周围的多个环状部分和多个带状部分， 形成在环形部分之间的用于连接环形部分的圆形部分; 以及形成在每个导电柱的暴露端上的UBM层，并且在导电柱的暴露端的周围的环形部分上延伸，由此有效地减少了应力以防止半导体插入件的翘曲。

公开(公告)号：US20150303138A1

公开(公告)日：2015-10-22

申请号：US14515970

申请日：2014-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jyun-Ling Tsai ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer.

Abstract translation: 提供了一种半导体插入器，其包括：具有限定有内部区域的表面和围绕内部区域的周边区域的基板; 多个导电柱，其嵌入到所述基板主体中，并且每个具有从所述基板主体的表面露出的一端; 形成在所述基板主体的表面上并且具有形成在所述周边区域中的周边部分的钝化层，形成在所述内部区域中的所述导电柱的暴露端的周围的多个环状部分和多个带状部分， 形成在环形部分之间的用于连接环形部分的圆形部分; 以及形成在每个导电柱的暴露端上的UBM层，并且在导电柱的暴露端的周围的环形部分上延伸，由此有效地减少了应力以防止半导体插入件的翘曲。