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公开(公告)号：US06239702B1
公开(公告)日：2001-05-29
申请号：US09038251
申请日：1998-03-10
IPC分类号： G08B1318
CPC分类号： H01L31/1125
摘要： The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.
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公开(公告)号：US06323768B2
公开(公告)日：2001-11-27
申请号：US09756808
申请日：2001-01-09
IPC分类号： G08B1318
CPC分类号： H01L31/1125
摘要： The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.
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公开(公告)号：US4866658A
公开(公告)日：1989-09-12
申请号：US244549
申请日：1988-09-12
申请人： Moshe Mazin , Dennis A. Henlin , Edward T. Lewis
发明人： Moshe Mazin , Dennis A. Henlin , Edward T. Lewis
CPC分类号： G06F7/503 , G06F2207/3876
摘要： A high speed full adder circuit is shown to include logic circuitry responsive to the levels of the two digital signals to be added for: (a) immediately producing an appropriate carry signal when the levels of the digital signals are the same; and (b) inverting the carry signal into such adder when the levels of the digital signals differ.
摘要翻译： 高速全加器电路被示为包括逻辑电路，其响应于要添加的两个数字信号的电平：（a）当数字信号的电平相同时立即产生适当的进位信号; 和（b）当数字信号的电平不同时，将进位信号转换成这样的加法器。
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公开(公告)号：US5002897A
公开(公告)日：1991-03-26
申请号：US406644
申请日：1989-09-13
申请人： Edward T. Lewis , Dale L. Montrone
发明人： Edward T. Lewis , Dale L. Montrone
IPC分类号： H01L27/095
CPC分类号： H01L27/095
摘要： A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.
摘要翻译： 称为互补金属电极半导体（CMES）的半导体器件具有在衬底上互连的p型和n型硅MESFET，其中p型MESFET的p沟道中注入n型势垒增强。 提供了制造结构和方法，用于形成具有非常低功率，低电压，低噪声和高速特性的CMES逻辑逆变器。
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公开(公告)号：US4704701A
公开(公告)日：1987-11-03
申请号：US667198
申请日：1984-11-01
申请人： Moshe Mazin , Edward T. Lewis
发明人： Moshe Mazin , Edward T. Lewis
CPC分类号： G06F7/507 , G06F2207/3876
摘要： A multibit digital adder wherein a proper carry-out signal is generated simultaneously in different parts of such adder.
摘要翻译： 一种多位数字加法器，其中在这种加法器的不同部分中同时产生适当的进位信号。
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公开(公告)号：US4797579A
公开(公告)日：1989-01-10
申请号：US78142
申请日：1987-07-27
申请人： Edward T. Lewis
发明人： Edward T. Lewis
IPC分类号： H03K19/0185 , H03K4/94 , H03K17/16 , H03K17/687 , H03K19/0175
CPC分类号： H03K4/94 , H03K17/6872
摘要： A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.
摘要翻译： CMOS输出驱动器具有精确控制从VLSI半导体芯片上的输出驱动器产生的信号的上升和下降时间。 两个时间依赖的电压发生器为CMOS反相器电路的每个栅极提供单独的斜坡信号。 每个电压发生器的斜坡信号特性由对已知电容充电的受控电流源的组合确定。
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公开(公告)号：US4675838A
公开(公告)日：1987-06-23
申请号：US667199
申请日：1984-11-01
申请人： Moshe Mazin , Edward T. Lewis
发明人： Moshe Mazin , Edward T. Lewis
CPC分类号： G06F7/507
摘要： A multibit digital adder is shown wherein a pair of carry generating circuitries is disposed between single adders for each bit in the digital numbers to be added, each one of such carry generating circuitries being responsive to a different carry-in signal and to the level of the bits applied to the associated single bit adder to produce the proper carry-in signal to the following single bit adder.
摘要翻译： 示出了一种多位数字加法器，其中在要添加的数字数字中的每个位的单个加法器之间设置一对进位产生电路，这些进位生成电路中的每一个响应于不同的进位输入信号和 这些位应用于相关联的单位加法器，以产生适当的进位信号给以后的单位加法器。
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8.发明授权
公开(公告)号：US5317214A
公开(公告)日：1994-05-31
申请号：US28511
申请日：1993-03-09
申请人： Edward T. Lewis
发明人： Edward T. Lewis
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/018528 , H03K19/018521
摘要： An interface circuit for converting a differential input voltage, having a common-mode level within a first range, into a differential output voltage having a different, common-mode level. The circuit feeds current between a pair of variable current sources and a pair of input terminals adapted to receive the differential input voltage through a pair of resistors. The amount of current passing through the pair of resistors is related to the common-mode level of the input signal. The resistors produce the differential output voltage at the pair of output terminals with a common-mode level related to the common-mode level of the input voltage translated an amount related to the amount of current passing through them.
摘要翻译： 一种用于将具有在第一范围内的共模电平的差分输入电压转换成具有不同共模电平的差分输出电压的接口电路。 电路在一对可变电流源和一对输入端之间馈电，适于通过一对电阻接收差分输入电压。 通过该对电阻器的电流量与输入信号的共模电平有关。 电阻器在一对输出端子处产生差分输出电压，其中共模电平与输入电压的共模电平相关，转换成与通过它们的电流量相关的量。
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公开(公告)号：US4951114A
公开(公告)日：1990-08-21
申请号：US279735
申请日：1988-12-05
申请人： Edward T. Lewis , Dale L. Montrone
发明人： Edward T. Lewis , Dale L. Montrone
IPC分类号： H01L27/095
CPC分类号： H01L27/095
摘要： A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.
摘要翻译： 称为互补金属电极半导体（CMES）的半导体器件具有在衬底上互连的p型和n型硅MESFET，其中p型MESFET的p沟道中注入n型势垒增强。 提供了制造结构和方法，用于形成具有非常低功率，低电压，低噪声和高速特性的CMES逻辑逆变器。
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公开(公告)号：US4856035A
公开(公告)日：1989-08-08
申请号：US199831
申请日：1988-05-26
申请人： Edward T. Lewis
发明人： Edward T. Lewis
CPC分类号： H03K23/56 , H03K23/52 , H03K3/037 , H03K3/35606 , H03K3/356078
摘要： A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.
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