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公开(公告)号：US06452459B1
公开(公告)日：2002-09-17
申请号：US09737996
申请日：2000-12-14
IPC分类号： H03B502
CPC分类号： G11C29/028 , G11C29/50 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge. In another embodiment, the RAM cells are arranged in a loop so that the sequence of RAM cells forms a ring oscillator, the period of which provides an indication of the time required for the RAM cells to store data in response to clock edges.
摘要翻译： 电路通过可编程逻辑器件上的一系列存储单元测量信号传播延迟。 在一个实施例中，多个RAM单元被串联配置。 每个RAM单元被初始化以存储逻辑0。 然后对第一RAM单元进行计时，使得RAM单元的输出上升到逻辑1。 从RAM单元的输出产生的上升沿然后对第二RAM单元进行计时，第二RAM单元又对该系列中的下一个RAM单元进行时钟。 上升沿遍历整个锁存器序列所需的时间是每个RAM单元的输出响应于时钟边沿而改变所需的累积时间。 因此，通过一系列RAM单元的延迟提供了一个RAM单元响应于时钟边沿来存储数据所需的时间的量度。 在另一个实施例中，RAM单元被布置成循环，使得RAM单元的序列形成环形振荡器，其周期提供RAM单元响应于时钟边沿而存储数据所需的时间的指示。
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2.发明授权Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product 有权使设计功能能够在集成电路装置和计算机程序产品中实现的方法公开(公告)号：US08155907B1
公开(公告)日：2012-04-10
申请号：US12480488
申请日：2009-06-08
CPC分类号： G06F17/5045 , G06F11/26 , G06F2217/86
摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.
摘要翻译： 公开了在集成电路装置中实现设计功能的方法。 示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。 还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。
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公开(公告)号：US5956257A
公开(公告)日：1999-09-21
申请号：US40738
申请日：1993-03-31
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
摘要翻译： 一种自动优化集成电路单元的分级网表的方法，包括至少一个包含较低层级的多个辅助单元的上级单元，包括接收定义所述网表和为其定时约束的数据，以及建立抽象定时模型 辅助细胞。 定时约束被传播到至少一个所选择的辅助小区，并且该小区通过平坦优化器被优化以产生所选择的辅助小区的优化版本。 所选单元格的优化版本插入到网表中。 时序约束表示单元输入端的信号的到达时间和单元输出端的信号的所需时间，单元的每个抽象定时模型包括定时参数，这些定时参数使单元格的指定输入与指定输出之间的延迟时间 的计算单元格。
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公开(公告)号：US06232845B1
公开(公告)日：2001-05-15
申请号：US09360350
申请日：1999-07-22
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516 , G01R31/31937 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.
摘要翻译： 电路通过一系列存储器元件测量信号传播延迟。 在一个实施例中，存储器元件被串联构造，使得它们一起形成延迟电路。 在另一个实施例中，存储器元件被配置成环路以形成环形振荡器。 每个存储器元件将信号传播到后续存储器元件，使得信号经过所有存储器元件的时间与由各个元件引起的平均延迟成比例。 这种相称性为测量这些部件的延迟提供了有效手段。 本发明的各种实施例测量存储器元件可被预置，清除，写入，读取或启用时钟的速度。
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5.发明授权Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates 失效用于在没有特定模板的电路的HDL描述中识别触发器的方法和装置
公开(公告)号：US5854926A
公开(公告)日：1998-12-29
申请号：US376491
申请日：1995-01-23
CPC分类号： G06F17/5045
摘要： A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals. The symbolic hardware implementations for each net can then be optimized using well-known techniques, and a netlist generated therefrom for purposes of creating masks for manufacturing the circuit. The invention can be easily implemented within known symbolic simulator routines already capable of synthesizing level-sensitive behavior using combinational logic.
摘要翻译： 公开了一种用于从电路的HDL描述检测边缘敏感行为的方法和装置，并且推断出具有异步设置和清除输入的广义边缘触发D型触发器的该行为的硬件实现。 本发明检测来自定向非循环图（DAGS）的边缘敏感行为，其表示电路的各个信号网络受电路HDL描述中定义的每个过程的影响。 然后，本发明修改每个DAG以推断控制广义触发器以模拟由DAG表示的网络的行为所需的异步控制表达式和数据输入表达式。 然后，本发明使用D型触发器和产生推断的控制信号所必需的任何组合逻辑来创建网络行为的符号硬件实现。 然后可以使用众所周知的技术来优化每个网络的符号硬件实现，以及为此创建用于制造用于制造电路的掩模的网表。 本发明可以容易地在已经能够使用组合逻辑合成水平敏感行为的已知符号仿真程序中实现。
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6.发明授权Scheduling processes in simulation of a circuit design based on simulation costs and runtime states of HDL processes 有权基于HDL过程的仿真成本和运行时状态的电路设计仿真中的调度过程公开(公告)号：US08768678B1
公开(公告)日：2014-07-01
申请号：US13245174
申请日：2011-09-26
CPC分类号： G06F9/4881 , G06F17/5009
摘要： One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.
摘要翻译： 一个或多个实施例提供用于改善并行HDL模拟器的运行时性能的负载平衡解决方案。 在编译期间，分析每个过程以基于HDL过程的复杂度来确定模拟成本。 在仿真期间，使用在编译时计算的仿真成本来调度在相同模拟周期中执行的过程，以减少模拟期间产生的延迟。
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公开(公告)号：US08386983B1
公开(公告)日：2013-02-26
申请号：US12853810
申请日：2010-08-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5077
摘要： In one embodiment, a method for parallel routing of a circuit design is provided. Placement of a netlist of the circuit design is determined for a target device. A plurality of regions of the target device is defined. Each region of the plurality of regions is assigned to a respective set of processors, each set including at least one processor. Global routing of nets of the netlist on the target device is performed. The global routing of each net restricts the net to one or more possible routes through a corresponding subset of the plurality of regions. Local routing of the netlist is concurrently performed within the plurality of regions using the respective sets of processors. Within each region, the local routing of the netlist is performed exclusively by the respective set of one or more processors.
摘要翻译： 在一个实施例中，提供了一种用于并行路由电路设计的方法。 为目标设备确定电路设计网表的位置。 定义目标设备的多个区域。 将多个区域中的每个区域分配给相应的处理器集合，每个处理器集合包括至少一个处理器。 执行目标设备上网表的网络的全局路由。 每个网络的全局路由将网络限制到通过多个区域的相应子集的一个或多个可能的路由。 使用各组处理器在多个区域内同时执行网表的本地路由。 在每个区域内，网表的本地路由由相应的一个或多个处理器集合执行。
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公开(公告)号：US06882182B1
公开(公告)日：2005-04-19
申请号：US10669589
申请日：2003-09-23
摘要： A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.
摘要翻译： 可调谐时钟分配系统用于最小化集成电路中时钟分配网络的功耗。 可调时钟分配系统在时钟分配网络上提供可调电感，以调节可调时钟分配系统中的谐振频率。 调谐电感使得可调谐时钟分配系统的谐振频率接近时钟分配网络上时钟信号的频率。 随着可调谐时钟分配系统的谐振频率接近时钟信号的频率，时钟分配网络的功耗降低。 一些实施例还在时钟分配网络上提供可调谐电容以调节可调时钟分配系统的谐振频率。
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公开(公告)号：US6144262A
公开(公告)日：2000-11-07
申请号：US360288
申请日：1999-07-22
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G01R31/3193 , G01R27/28 , G04F10/02 , H03B5/02 , H03H11/26
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/31937 , G11C29/028 , G11C29/50012 , G01R31/318516
摘要： A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal. In another embodiment, the latches are arranged in a loop so that the sequence of latches forms a ring oscillator, the period of which provides an indication of the time required for the latches to respond to clock-enable signals. Other embodiments include sequences of flip-flops arranged as delay elements or ring oscillators. Those embodiments provide means for measuring the time required for flip-flops to respond to preset or clear signals.
摘要翻译： 电路通过可编程逻辑器件上的一系列存储器元件测量信号传播延迟。 在一个实施例中，多个锁存器被串联配置。 每个锁存器被初始化以存储一个逻辑0。 然后，第一个锁存器被使能时钟使得锁存器的输出上升到逻辑1。 来自第一锁存时钟的逻辑电路使得串联中的第二锁存器能够使得第二锁存器的输出上升到逻辑1，这又使得串联中的下一个锁存器成为逻辑1。 上升沿遍历整个锁存序列所需的时间是每个锁存器的输出响应于时钟使能信号而变化所需的累积时间。 因此，通过一系列锁存器的延迟提供了一个锁存器响应时钟使能信号所需的时间的量度。 在另一个实施例中，锁存器被布置成环路，使得锁存器序列形成环形振荡器，其周期提供锁存器响应时钟使能信号所需的时间的指示。 其他实施例包括布置为延迟元件或环形振荡器的触发器序列。 这些实施例提供了用于测量触发器响应预设或清除信号所需的时间的装置。
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10.发明授权Method and system for measuring signal propagation delays using the duty cycle of a ring oscillator 失效使用环形振荡器的占空比测量信号传播延迟的方法和系统
公开(公告)号：US6069849A
公开(公告)日：2000-05-30
申请号：US115138
申请日：1998-07-14
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。 最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。 相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。 然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。
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