公开(公告)号：US06228780B1

公开(公告)日：2001-05-08

申请号：US09318957

申请日：1999-05-26

申请人： So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

发明人： So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

IPC分类号： H01L2131

CPC分类号： H01L28/40 ,  H01L21/3185 ,  H01L28/56 ,  Y10S438/958

摘要： A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed. Completion of fabrication includes thermal processing. Voids are not formed within the metal lines because the non-shrinkable passivation layer does not shrink during the thermal processing.

摘要翻译： 描述了一种形成不会收缩的金属钝化层的新方法，其将消除金属空隙并提高集成电路器件的电迁移寿命。 半导体器件结构设置在半导体衬底中并在半导体衬底上并被绝缘层覆盖。 沉积在绝缘层上的金属层被图案化以形成金属线，其中在两条金属线之间存在间隙。 根据以下步骤形成不可收缩的钝化层：1）将HDP-CVD氧化物层沉积在金属线上，其中间隙由HDP-CVD氧化物层填充。 2）通过覆盖HDP-CVD氧化物层的等离子体增强化学气相沉积沉积氮化硅层。 或者，1）在金属线上沉积PECVD氧化物层。 2）通过PECVD在氧化物层上沉积氮化硅层以填充间隙并完成钝化。 然后，完成集成电路装置的制造。 制造完成包括热处理。 由于在热处理期间不可收缩的钝化层不收缩，所以在金属线内不形成空隙。

公开(公告)号：US6140603A

公开(公告)日：2000-10-31

申请号：US283000

申请日：1999-03-31

申请人： Ruey-Lian Hwang ,  Yung-Sheng Huang

发明人： Ruey-Lian Hwang ,  Yung-Sheng Huang

IPC分类号： B23K26/40 ,  H01L21/304 ,  B23K26/00

CPC分类号： H01L21/3043 ,  B23K26/362 ,  B23K26/40 ,  B23K2203/50

摘要： A micro-cleavage method for preparing a semiconductor specimen for examination by an optical or electron microscopic is disclosed. The method can be carried out by hand and thus no expensive equipment such as a polishing machine is necessary. In the method, at least two bird's beak marks are cut in a top surface of a silicon wafer that contains a target, i.e., a defect or a circuit to be examined. The bird's beak marks are formed by a wide scribe line and a narrow scribe line overlapped together. The wide scribe line of the bird's beak mark is used for visual alignment with the edge of a rigid substrate, while the fine scribe line is utilized for initiating a crack when a bending stress is applied on the bird's beak mark. The bird's beak mark can be made by using a laser cutter after a wafer slice which contains the target area is first cleaved by mechanical means such as a diamond knife. A first bird's beak mark is formed at the cleaved edge of the slice and a second bird's beak mark is formed with its fine scribe line oriented toward the target. When a bending stress is applied on the top surface of the silicon slice, stress concentrates on the bird's beak marks and creates a fine crack to propagate along a crystallographic plane in the wafer toward the target thus exposing the target in a fractured surface.

摘要翻译： 公开了一种通过光学或电子显微镜制备用于检查的半导体样品的微裂纹方法。 该方法可以手工进行，因此不需要昂贵的设备如抛光机。 在该方法中，在包含目标物，即缺陷或待检查的电路的硅晶片的顶表面中切割至少两个鸟的喙标记。 鸟的喙标记由宽的划线和狭窄的划线重叠在一起形成。 鸟喙标记的宽划线用于与刚性基底的边缘的视觉对准，而当在鸟的喙标记上施加弯曲应力时，细切割线用于引发裂纹。 可以通过使用激光切割机在包含目标区域的晶片切片之后首先用诸如金刚石刀等机械手段切割来制作鸟的喙标记。 在切片的切割边缘处形成第一只鸟的喙标记，并且形成第二个鸟的喙标记，其细的划线朝向目标。 当在硅片的顶表面上施加弯曲应力时，应力集中在鸟的喙痕上，并产生细小的裂纹，沿着晶片中的晶面朝向靶传播，从而将目标暴露在断裂的表面中。

公开(公告)号：US5933704A

公开(公告)日：1999-08-03

申请号：US865847

申请日：1997-06-02

申请人： Ruey-Lian Hwang ,  Yung-Sheng Huang ,  Chin-Cheng Chiu

发明人： Ruey-Lian Hwang ,  Yung-Sheng Huang ,  Chin-Cheng Chiu

IPC分类号： H01L21/66 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L22/24 ,  H01L23/522 ,  H01L2924/0002

摘要： A new method of preparing for inspection a wafer having multilayer interconnections is described. Semiconductor device structures having multilayer interconnections are provided in and on a semiconductor substrate wherein the multilayer interconnections comprise alternating layers of oxide interlevel dielectric layers and conducting layers and wherein interconnections are made between the conducting layers through the interlevel dielectric layers and wherein a non-oxide passivation layer overlies the topmost dielectric layer. The non-oxide passivation layer is removed and an oxide passivation layer is deposited overlying the topmost dielectric layer. The oxide passivation layer and interlevel dielectric layers and conducting layers are cut through to expose a sidewall to reveal the multilayer interconnections. The interlevel dielectric layers between conducting layers in the area of the exposed sidewall are removed to complete preparation for observing the semiconductor wafer having multilayer interconnections.

摘要翻译： 描述了一种准备检查具有多层互连的晶片的新方法。 具有多层互连的半导体器件结构设置在半导体衬底中和半导体衬底上，其中多层互连包括氧化物层间电介质层和导电层的交替层，并且其中通过层间电介质层在导电层之间形成互连，并且其中非氧化物钝化 层覆盖在最上面的介电层上。 除去非氧化物钝化层，并将氧化物钝化层沉积在最上面的介电层上。 切割氧化物钝化层和层间电介质层和导电层以露出侧壁以露出多层互连。 在暴露的侧壁的区域中的导电层之间的层间电介质层被去除以完成用于观察具有多层互连的半导体晶片的准备。

公开(公告)号：US06306750B1

公开(公告)日：2001-10-23

申请号：US09483934

申请日：2000-01-18

申请人： Yung-Sheng Huang ,  Chiu-Ching Lin ,  Chun-Hung Lu ,  Ruey-Lian Hwang

发明人： Yung-Sheng Huang ,  Chiu-Ching Lin ,  Chun-Hung Lu ,  Ruey-Lian Hwang

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2224/78 ,  H01L2924/00

摘要： A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying the bond pad structure, while overlying, and contacting, an underlying upper level, metal interconnect structure. The use of a tungsten mesh pattern, in place of individual tungsten studs, results in the creation of isolated islands, of IMED, reducing the bonding force, experienced by the IMD shapes, during the subsequent gold wire bond procedure. In addition the tungsten mesh pattern is formed via partial filling of a mesh pattern opening, in the IMD layer, resulting in an indented, or notched top surface. This in turn allows a roughened top surface, for the overlying bond pad structure, to be created, resulting in improved bondability of the gold wire, to the roughened top surface of the bond pad structure.

摘要翻译： 已经开发了一种形成具有粗糙顶表面形貌的接合焊盘结构的方法，其用于改善金线键合的粘合性，使其成为下面的焊盘结构。 该方法的特征在于，形成在IMD层中并且位于接合焊盘结构下方的钨网状图案的使用，同时覆盖和接触下层的金属互连结构。 在随后的金丝焊接过程中，使用钨网格图代替单独的钨螺柱，导致产生IMED的隔离岛，从而降低IMD形状所经受的结合力。 此外，在IMD层中，通过部分填充网状图案开口形成钨网格图案，导致凹陷或缺口的顶部表面。 这又允许产生用于覆盖的焊盘结构的粗糙的顶表面，从而提高金线与接合焊盘结构的粗糙化顶表面的粘合性。