公开(公告)号：US5709755A

公开(公告)日：1998-01-20

申请号：US694728

申请日：1996-08-09

Applicant: So Wein Kuo ,  Tsu Shih ,  Chung-Long Chang

Inventor： So Wein Kuo ,  Tsu Shih ,  Chung-Long Chang

IPC: B08B1/04 ,  H01L21/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/30

CPC classification number: H01L21/02052 ,  B08B1/04 ,  H01L21/02024 ,  H01L21/67046

Abstract: Using an APM solution to clean both the front and backside of a semiconductor wafer significantly reduces the residue from chemical mechanical polishing. A low residue count holds the wafer more securely to the electrostatic chuck, thus improving processing, reducing wear on the electrostatic chuck, and increasing its lifetime.

Abstract translation: 使用APM解决方案清洁半导体晶片的正面和背面显着减少化学机械抛光的残留物。 低残留数量将晶片更牢固地保持在静电卡盘上，从而改善处理，减少静电卡盘上的磨损，并延长其使用寿命。

公开(公告)号：US06287926B1

公开(公告)日：2001-09-11

申请号：US09253297

申请日：1999-02-19

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06228780B1

公开(公告)日：2001-05-08

申请号：US09318957

申请日：1999-05-26

Applicant: So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

Inventor： So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

IPC: H01L2131

CPC classification number: H01L28/40 ,  H01L21/3185 ,  H01L28/56 ,  Y10S438/958

Abstract: A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed. Completion of fabrication includes thermal processing. Voids are not formed within the metal lines because the non-shrinkable passivation layer does not shrink during the thermal processing.

Abstract translation: 描述了一种形成不会收缩的金属钝化层的新方法，其将消除金属空隙并提高集成电路器件的电迁移寿命。 半导体器件结构设置在半导体衬底中并在半导体衬底上并被绝缘层覆盖。 沉积在绝缘层上的金属层被图案化以形成金属线，其中在两条金属线之间存在间隙。 根据以下步骤形成不可收缩的钝化层：1）将HDP-CVD氧化物层沉积在金属线上，其中间隙由HDP-CVD氧化物层填充。 2）通过覆盖HDP-CVD氧化物层的等离子体增强化学气相沉积沉积氮化硅层。 或者，1）在金属线上沉积PECVD氧化物层。 2）通过PECVD在氧化物层上沉积氮化硅层以填充间隙并完成钝化。 然后，完成集成电路装置的制造。 制造完成包括热处理。 由于在热处理期间不可收缩的钝化层不收缩，所以在金属线内不形成空隙。

公开(公告)号：US6063695A

公开(公告)日：2000-05-16

申请号：US192451

申请日：1998-11-16

Applicant: Chung-Te Lin ,  Chin-Hsiung Ho ,  Hsueh-Liang Chiu ,  So-Wein Kuo

Inventor： Chung-Te Lin ,  Chin-Hsiung Ho ,  Hsueh-Liang Chiu ,  So-Wein Kuo

IPC: H01L21/304 ,  H01L23/544 ,  H01L21/301

CPC classification number: H01L23/544 ,  H01L21/3043 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S148/028 ,  Y10S438/94

Abstract: A process for the formation of deep clear laser marks on silicon wafers is described. Tall ridges of material which is erupted from the wafer surface during the deep laser penetration form adjacent to the marks. These ridges are of the order of 3 to 15 microns in height and must be removed prior to subsequent wafer processing to avoid fragmentation causing scratches and particulate contamination. The process of the invention deposits a non-conformal layer of photoresist or other flowable material on the wafer. The peaks of the ridges protrude above the surface of the conformal layer be a significant amount and are then etched away using an aqueous silicon etch. The non-conformal layer protects the wafer surface from the silicon etch so that only the ridges are removed. After the ridges are etched, the non-conformal layer is removed leaving residual ridges of a height less than or equal to the thickness of the conformal layer.

Abstract translation: 描述了在硅晶片上形成深度清晰的激光标记的工艺。 在深度激光穿透期间从晶片表面喷出的与标记相邻的材料的高隆起。 这些脊的高度为3至15微米的数量级，并且必须在随后的晶片加工之前被去除，以避免碎片引起划痕和颗粒污染。 本发明的方法在晶片上沉积光致抗蚀剂或其它可流动材料的非共形层。 突起在保形层表面之上的脊的峰值是相当大的量，然后使用含水硅蚀刻蚀刻掉。 非保形层保护晶片表面免受硅蚀刻，从而仅去除脊。 在蚀刻脊之后，去除非共形层，留下高度小于或等于共形层厚度的残留脊。

公开(公告)号：US5661084A

公开(公告)日：1997-08-26

申请号：US725808

申请日：1996-10-04

Applicant: So Wein Kuo ,  Tsu Shih

Inventor： So Wein Kuo ,  Tsu Shih

IPC: H01L21/311 ,  H01L21/283 ,  H01L21/31

CPC classification number: H01L21/31144

Abstract: A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening. The substrate is dipped into a hydrofluoric acid solution to remove the native oxide on the sidewalls of the contact opening whereby the hydrofluoric acid etches the BPTEOS layer at a slower rate than it etches the first and third TEOS layers whereby the contact profile is made vertical. A glue layer is sputter deposited over the surface of the insulating layer structure and within the contact opening. A conducting layer is deposited over the glue layer filling the contact opening completing the electrical contact in the fabrication of the integrated circuit device.

Abstract translation: 描述了一种用于制造用于CMOS或其他集成电路的接触或通孔开口和填充冶金的方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 在其上形成绝缘层结构，其中包括第一层四乙氧基硅烷（TEOS），第二层硼磷-POOS（BPTEOS）和第三层TEOS。 通过未被掩模覆盖的绝缘层结构蚀刻接触开口到要电接触的半导体器件结构，其中由于BPTEOS层被蚀刻，接触开口的轮廓不垂直。 水平地多于第一和第三TEOS层，并且其中天然氧化物积聚在接触开口的侧壁上。 将基底浸入氢氟酸溶液中以除去接触开口侧壁上的天然氧化物，由此氢氟酸以比蚀刻第一和第三TEOS层更慢的速率蚀刻BPTEOS层，从而使接触轮廓垂直。 在绝缘层结构的表面上和接触开口内溅射沉积胶层。 在集成电路器件的制造中，导电层沉积在填充接触开口的胶层上，完成电接触。

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US5854137A

公开(公告)日：1998-12-29

申请号：US638666

申请日：1996-04-29

Applicant: So Wein Kuo

Inventor： So Wein Kuo

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/02071 ,  H01L21/32137

Abstract: An improved method of plasma-activated reactive subtractive etching of polycide layers by mixtures of sulfur hexafluoride, hydrogen bromide, and oxygen gases is achieved. After the subtractive etching of the polycide layer is performed, a purging operation of the reaction chamber by admission of a non-reactive gas such as nitrogen followed by evacuation results in the removal of water vapor and other residual species. This purging step inhibits the formation of needle-like crystals of residual compounds thought to form by chemical reaction between hydrogen bromide and water vapor and other species. Such needle-like crystalline residues can be construed as defects in the etched polycide patterns, and their minimization results in increased manufacturing yields after visual inspection. Additionally, the reduced incidence of residual crystalline residues is beneficial in helping to improve subsequent integrated circuit reliability.

Abstract translation: 实现了通过六氟化硫，溴化氢和氧气的混合物等离子体激活的反应性消减蚀刻改性方法。 在进行多阴离子层的减去蚀刻之后，通过进入诸如氮气之类的非反应性气体进行抽气操作，导致反应室的清除操作导致水蒸气和其它残留物质的去除。 该清洗步骤抑制被认为通过溴化氢和水蒸气等物质之间的化学反应形成的残留化合物的针状晶体的形成。 这种针状晶体残留物可以解释为蚀刻的多晶硅化合物图案中的缺陷，并且它们的最小化导致目视检查后增加的制造产量。 此外，残留结晶残余物的降低的发生率有助于有助于提高随后的集成电路可靠性。

公开(公告)号：US06790756B2

公开(公告)日：2004-09-14

申请号：US10385954

申请日：2003-03-11

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

IPC: H01L213205

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06468918B1

公开(公告)日：2002-10-22

申请号：US08536485

申请日：1995-09-29

Applicant: So Wein Kuo

Inventor： So Wein Kuo

IPC: H01L213065

CPC classification number: H01L21/67173 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/67201 ,  H01L21/67225

Abstract: An apparatus and method for the hot bake to remove moisture from photoresist that has been deposited on semiconductor wafers prior to a dry plasma etch process. A wafer carrier containing semiconductor wafers on which a photoresist has been deposited is placed in a load lock chamber having a source of heat such as a heating plate or a high intensity light source. The source of the heat is activated and the semiconductor wafers are brought to a temperature sufficiently high and of a sufficient duration as to eliminate any moisture present in the photoresist mask. The load lock chamber is evacuated to eliminate any moisture or contaminants, filled with nitrogen to eliminate any residual of moisture or contaminants, and then evacuated to prepare the chamber to exposed to the atmosphere present in a dry plasma etch chamber. An exit lock of the load lock chamber is opened and the wafer carrier is placed in the dry plasma etch chamber for the execution of the dry plasma etch process.

Abstract translation: 一种用于热干燥从干法等离子体蚀刻工艺之前沉积在半导体晶片上的光致抗蚀剂去除水分的设备和方法。 含有其上沉积有光致抗蚀剂的半导体晶片的晶片载体被放置在具有加热板或高强度光源的热源的加载锁定室中。 热源被激活，半导体晶片的温度足够高并具有足够的持续时间，以消除光致抗蚀剂掩模中存在的任何水分。 将负载锁定室抽真空以消除填充有氮气的任何水分或污染物，以消除任何残留的水分或污染物，然后抽真空以制备室以暴露于存在于干等离子体蚀刻室中的气氛中。 打开负载锁定室的出口锁，将晶片载体放置在干式等离子体蚀刻室中，以执行干等离子体蚀刻工艺。

公开(公告)号：US5872061A

公开(公告)日：1999-02-16

申请号：US958429

申请日：1997-10-27

Applicant: Shing-Long Lee ,  Chia Shiung Tsai ,  So Wein Kuo

Inventor： Shing-Long Lee ,  Chia Shiung Tsai ,  So Wein Kuo

IPC: H01L21/311 ,  H01L21/302

CPC classification number: H01L21/02063 ,  H01L21/31116

Abstract: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

Abstract translation: 一种用于在微电子学制造中形成图案化含氟等离子体蚀刻层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成含氟等离子体可蚀刻层。 然后在含氟等离子体可蚀刻层上形成图案化的光致抗蚀剂层。 然后通过含氟等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为含氟等离子体可蚀刻层的光致抗蚀剂蚀刻掩模层，以形成图案化含氟等离子体蚀刻层。 图案化的含氟等离子体蚀刻层在其上形成有氟聚合物残留层。 含氟等离子体蚀刻方法使用包含三氟化氮蚀刻剂气体的第一蚀刻剂气体组合物。 最后，通过含氧等离子体剥离方法从图案化的含氟等离子体蚀刻层剥离图案化的光致抗蚀剂层和含氟聚合物残余物层。 含氧等离子体汽提方法采用包含含氟蚀刻剂气体和含氧蚀刻剂气体的第二蚀刻剂气体组合物。