公开(公告)号：US20250006258A1

公开(公告)日：2025-01-02

申请号：US18883220

申请日：2024-09-12

Applicant: Socionext Inc.

Inventor： Shinichi MORIWAKI

IPC: G11C11/419 ,  G11C11/412

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells each connected to a bit line pair; and a write circuit that brings a low potential-side bit line to a negative potential in response to a negative potential boost signal. At the data read operation, a word line is activated after a lapse of a first predetermined time from a transition of an input clock signal, to read the memory value of the memory cell. At the data write operation, the word line is activated after a lapse of a second predetermined time longer than the first predetermined time from a transition of the input clock signal, and the negative potential boost signal is activated after a lapse of a third predetermined time longer than the first predetermined time.

公开(公告)号：US20210074713A1

公开(公告)日：2021-03-11

申请号：US16950644

申请日：2020-11-17

Applicant: SOCIONEXT INC.

Inventor： Shinichi MORIWAKI

IPC: H01L27/112 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78

Abstract: In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

公开(公告)号：US20200043554A1

公开(公告)日：2020-02-06

申请号：US16511604

申请日：2019-07-15

Applicant: SOCIONEXT INC.

Inventor： Shinichi MORIWAKI

IPC: G11C15/04

Abstract: A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.

公开(公告)号：US20200372952A1

公开(公告)日：2020-11-26

申请号：US16993403

申请日：2020-08-14

Applicant: SOCIONEXT INC.

Inventor： Shinichi MORIWAKI

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/11

Abstract: In an SRAM cell using vertical nanowire (VNW) FETs, transistors (PD1, PD2) constituting a drive transistor are placed on both sides of a transistor (PU1) in an X direction, and transistors (PD3, PD4) constituting a drive transistor are placed on both sides of a transistor (PU2) in the X direction. An access transistor (PG1) is placed on one-hand side in the X direction of the transistor (PU1), and an access transistor (PG2) is placed on the other-hand side in the X direction of the transistor (PU1).

公开(公告)号：US20190267079A1

公开(公告)日：2019-08-29

申请号：US16407084

申请日：2019-05-08

Applicant: SOCIONEXT INC.

Inventor： Shinichi MORIWAKI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Disclosed is a semiconductor storage device having a dual-port SRAM cell with a smaller area and low-current consumption and securing a good static noise margin. The semiconductor storage device includes a memory cell circuit constituting the dual port SRAM cell comprised of six transistors. When driving the first or second word line, a word line driver circuit lowers a high-level voltage which is to be output to the driven word line such that the high-level voltage is lower than a high-level voltage which is to be output to both of the first and second word lines when driving both the first and second word lines.

公开(公告)号：US20240112746A1

公开(公告)日：2024-04-04

申请号：US18538722

申请日：2023-12-13

Applicant: SOCIONEXT INC.

Inventor： Yasumitsu SAKAI ,  Shinichi MORIWAKI

IPC: G11C17/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C17/12 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

公开(公告)号：US20220359541A1

公开(公告)日：2022-11-10

申请号：US17872810

申请日：2022-07-25

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI ,  Shinichi MORIWAKI

IPC: H01L27/11

Abstract: Nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

公开(公告)号：US20220093613A1

公开(公告)日：2022-03-24

申请号：US17539695

申请日：2021-12-01

Applicant: Socionext Inc.

Inventor： Shinichi MORIWAKI

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Transistors N1, N5 corresponding to a drive transistor PD1 are formed in a cell lower part and a cell upper part, respectively, and transistors N2, N6 corresponding to a drive transistor PD2 are formed in the cell lower part and the cell upper part, respectively. A transistor P1 corresponding to a load transistor PU2 is formed in the cell lower part, and a transistor P2 corresponding to a load transistor PU1 is formed in the cell upper part.

公开(公告)号：US20250157532A1

公开(公告)日：2025-05-15

申请号：US19022682

申请日：2025-01-15

Applicant: Socionext Inc.

Inventor： Shinichi MORIWAKI

IPC: G11C11/419 ,  G11C11/418

Abstract: A semiconductor memory device includes a memory cell array and a write circuit having a function of lowering the potential of a bit line connected to a write-target memory cell, and bringing the low potential-side bit line to a negative potential by means of a capacitance in response to a negative potential boost signal. The memory cell array includes a first memory bank and a second memory bank each having a plurality of memory cells. The low potential-side bit line is brought to a negative potential using only a first capacitor element at the time of write into the first memory bank, and using the first capacitor element and a second capacitor element at the time of write into the second memory bank.

公开(公告)号：US20240212724A1

公开(公告)日：2024-06-27

申请号：US18594877

申请日：2024-03-04

Applicant: Socionext Inc.

Inventor： Shinichi MORIWAKI

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C2207/065

Abstract: A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.