公开(公告)号：US20130228852A1

公开(公告)日：2013-09-05

申请号：US13600373

申请日：2012-08-31

申请人： Soichiro KITAZAKI ,  Masaru KIDOH ,  Mitsuru SATO ,  Ryota KATSUMATA ,  Tadashi IGUCHI

发明人： Soichiro KITAZAKI ,  Masaru KIDOH ,  Mitsuru SATO ,  Ryota KATSUMATA ,  Tadashi IGUCHI

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

公开(公告)号：US20120241844A1

公开(公告)日：2012-09-27

申请号：US13236833

申请日：2011-09-20

申请人： Tadashi IGUCHI ,  Ryota KATSUMATA

发明人： Tadashi IGUCHI ,  Ryota KATSUMATA

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L23/481 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：第一和第二堆叠体，第一和第二半导体柱，连接部分，存储膜和分隔绝缘层。 堆叠的栅极包括沿着第一轴线堆叠的电极膜和设置在电极膜之间的电极间绝缘膜。 在堆叠体中设置有通孔。 半导体柱被填充到通孔中。 连接部电连接半导体支柱。 存储膜设置在半导体柱和电极膜之间。 分隔绝缘层分隔第一和第二电极膜。 分隔绝缘层侧的第一通孔的侧面和分隔绝缘层侧的第二贯通孔的侧面具有与从第一层叠体到第二贯通孔的第二轴正交的平面的部分 第二堆叠体。

公开(公告)号：US20130234332A1

公开(公告)日：2013-09-12

申请号：US13600439

申请日：2012-08-31

申请人： Hiromitsu IINO ,  Tadashi IGUCHI

发明人： Hiromitsu IINO ,  Tadashi IGUCHI

IPC分类号： H01L23/48 ,  H01L21/48

CPC分类号： H01L23/481 ,  H01L21/486 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a plurality of contact electrodes, a plurality of first insulating portions, and a plurality of second insulating portions. The plurality of contact electrodes extends in a stacking direction of the stacked body. Each of the contact electrodes reaches corresponding one of the conductive layers. The plurality of first insulating portions respectively is provided between the plurality of contact electrodes and the stacked body. The plurality of second insulating portions respectively is provided between the plurality of first insulating portions and the stacked body.

摘要翻译： 根据一个实施例，半导体器件包括其中多个导电层和多个绝缘层交替堆叠的堆叠体。 半导体器件包括多个接触电极，多个第一绝缘部分和多个第二绝缘部分。 多个接触电极沿堆叠体的层叠方向延伸。 每个接触电极到达相应的一个导电层。 多个第一绝缘部分别设置在多个接触电极和层叠体之间。 多个第二绝缘部分别设置在多个第一绝缘部分和堆叠体之间。

公开(公告)号：US20090267138A1

公开(公告)日：2009-10-29

申请号：US12420584

申请日：2009-04-08

申请人： Tadashi IGUCHI

发明人： Tadashi IGUCHI

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L21/76224 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42352

摘要： A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed on the silicon substrate, a charge film formed on the tunnel insulating film, and a common block film formed on the charge film. The common block film is formed in common with the memory cells along first direction. An element isolation insulating film buried in the element isolation trench has an upper portion of a side wall of the element isolation insulating film which contacts with a side wall of the charge film in each of the memory cells and a top portion of the element isolation insulating film which contacts with the common block film. A control electrode film is formed on the common block film.

摘要翻译： 电荷陷阱型非易失性存储器件具有沿着第一方向延伸的元件隔离沟槽，以预定的间隔在硅衬底上形成存储单元。 每个存储单元具有形成在硅衬底上的隧道绝缘膜，形成在隧道绝缘膜上的电荷膜和形成在电荷膜上的公共阻挡膜。 公共阻挡膜与第一方向的存储单元共同形成。 埋在元件隔离沟槽中的元件隔离绝缘膜具有元件隔离绝缘膜的侧壁的上部，其与每个存储单元中的电荷膜的侧壁接触，并且元件隔离绝缘的顶部 与公共阻挡膜接触的膜。 在公共阻挡膜上形成控制电极膜。