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    Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration
    3.
    发明授权
    Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration 失效
    在硅硅衬底上制造具有平面氧化物/ SOI界面的局部厚盒，用于硅光子学集成

    公开(公告)号：US08772902B2

    公开(公告)日：2014-07-08

    申请号：US13451141

    申请日：2012-04-19

    申请人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

    IPC分类号： H01L21/70

    CPC分类号： G02B6/13 ,  H01L21/76232 ,  H01L21/76289

    摘要： Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate.

    摘要翻译： 线槽形成在体半导体衬底和不透氧层的堆叠中，使得体半导体衬底中的沟槽的深度大于一对相邻定位的线沟槽之间的横向间隔。 不透水间隔物形成在线沟槽的侧壁上。 单独或与氧化组合的各向同性蚀刻从氧不透性间隔物的下面去除半导体材料，以扩大线沟槽的扩展底部的横向范围，并且减小相邻扩展底部之间的横向间隔 。 底部周围的半导体材料被氧化以形成在多个不透氧隔离物下面的半导体氧化物部分。 半导体绝缘体（SOI）部分形成在半导体氧化物部分之上和体半导体衬底内。

    Germanium Photodetector
    4.
    发明申请
    Germanium Photodetector 有权
    锗光检测器

    公开(公告)号：US20120288992A1

    公开(公告)日：2012-11-15

    申请号：US13556597

    申请日：2012-07-24

    申请人： Solomon Assefa ,  Jeehwan Kim ,  Jin-Hong Park ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Jeehwan Kim ,  Jin-Hong Park ,  Yurii A. Vlasov

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1808 ,  H01L31/1085 ,  Y02E10/50

    摘要： A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer.

    摘要翻译： 一种形成光检测器件的方法包括：在基片上形成绝缘体层，在绝缘体层和一部分基底上形成锗（Ge）层，在Ge层上形成第二绝缘层，构图Ge层，形成 在所述第二绝缘体层上的封盖绝缘体层和所述第一绝缘体层的一部分，加热所述器件以使所述Ge层结晶，得到单晶Ge层，在所述单晶Ge层中注入n型离子，将所述器件加热至 在单晶Ge层中激活n型离子，以及形成电连接到单晶n型Ge层的电极。

    TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
    5.
    发明申请
    TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES 有权
    光电装置温度控制装置

    公开(公告)号：US20120125916A1

    公开(公告)日：2012-05-24

    申请号：US13363995

    申请日：2012-02-01

    申请人： Solomon Assefa ,  William M. Green ,  Young-hee Kim ,  Joris Van Campenhout ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  William M. Green ,  Young-hee Kim ,  Joris Van Campenhout ,  Yurii A. Vlasov

    IPC分类号： H05B6/02 ,  H01L21/329 ,  H01L29/66

    CPC分类号： H01L35/34 ,  G02B6/12004 ,  G02B6/1347 ,  G02B2006/12069 ,  G02F1/0147 ,  G02F1/025

    摘要： Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.

    摘要翻译： 电流可以通过n掺杂半导体区域，凹陷金属半导体合金部分和p掺杂半导体区域，使得掺杂半导体区域中的多数电荷载流子的扩散通过Peltier- 塞贝克效应。 此外，温度控制装置可以被配置为包括位于光电子器件附近的金属半导体合金区域，具有p型掺杂的第一半导体区域和具有n型掺杂的第二半导体区域。 因此可以控制光电子器件的温度以稳定光电器件的性能。

    Avalanche impact ionization amplification devices
    7.
    发明授权
    Avalanche impact ionization amplification devices 有权
    雪崩冲击电离放大装置

    公开(公告)号：US08395103B2

    公开(公告)日：2013-03-12

    申请号：US13455507

    申请日：2012-04-25

    申请人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    发明人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    IPC分类号： H01L31/00 ,  H01L31/107

    CPC分类号： H01L31/107 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  Y02E10/50

    摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

    摘要翻译： 半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。 半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。 多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增 光电检测机制或雪崩冲击电离电流放大机制。

    Avalanche impact ionization amplification devices
    9.
    发明授权
    Avalanche impact ionization amplification devices 有权
    雪崩冲击电离放大装置

    公开(公告)号：US08232516B2

    公开(公告)日：2012-07-31

    申请号：US12533521

    申请日：2009-07-31

    申请人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    发明人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    IPC分类号： H01L31/00 ,  H01L31/107

    CPC分类号： H01L31/107 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  Y02E10/50

    摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

    摘要翻译： 半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。 半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。 多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增 光电检测机制或雪崩冲击电离电流放大机制。

    Three-dimensional integrated circuits and techniques for fabrication thereof
    10.
    发明授权
    Three-dimensional integrated circuits and techniques for fabrication thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US07897428B2

    公开(公告)日：2011-03-01

    申请号：US12131988

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二键合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。