公开(公告)号：US5908307A

公开(公告)日：1999-06-01

申请号：US792107

申请日：1997-01-31

申请人： Somit Talwar ,  Karl-Josef Kramer ,  Guarav Verma ,  Kurt Weiner

发明人： Somit Talwar ,  Karl-Josef Kramer ,  Guarav Verma ,  Kurt Weiner

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L29/66575 ,  H01L21/2254 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/0847 ,  Y10S148/061

摘要： Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.

摘要翻译： 晶体硅表面层的超非晶化至超浅（例如，小于100nm）深度提供了制造问题的解决方案，包括（1）晶体硅中的高热传导和（2）阴影和衍射干涉效应 通过场效应晶体管已经制造的入射激光辐射的栅极。 过去这些问题已经阻止了现有技术的投影气体浸没激光掺杂在制造包含使用100nm和较浅结结技术的MOS场效应晶体管的集成电路中有效地使用。

公开(公告)号：US5888888A

公开(公告)日：1999-03-30

申请号：US791775

申请日：1997-01-29

申请人： Somit Talwar ,  Guarav Verma ,  Karl-Josef Kramer ,  Kurt Weiner

发明人： Somit Talwar ,  Guarav Verma ,  Karl-Josef Kramer ,  Kurt Weiner

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/22 ,  H01L21/24

CPC分类号： H01L29/66507 ,  H01L21/268 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L21/26506 ,  H01L21/26513

摘要： The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example. An insulator layer and a conductive lead can subsequently be patterned to establish electrical contact to the silicide region. The low contact resistivity of the silicide region provides the capability to transmit relatively high-frequency electronic signals through the contact region. In a preferred application, the invented method is used to form self-aligned silicide contact regions for the gate, source and drain of a metal-insulator-semiconductor field-effect transistor (MISFET).

摘要翻译： 本发明的方法在硅体上产生可用于各种目的的硅化物区域，包括降低与硅体或其上形成的集成电子器件的电接触电阻。 本发明的方法包括以下步骤：使用离子注入在硅体上产生非晶区域，例如形成或定位与非晶区域接触的诸如钛，钴或镍的金属，并用来自 例如，激光源使金属原子扩散到非晶区域。 因此，非晶区域成为具有所需硅化物组成的合金区域。 照射后冷却，合金区域变得部分结晶。 为了将合金区域转化为更结晶的形式，本发明的方法优选包括例如使用快速热退火处理合金区域的步骤。 随后可以对绝缘体层和导电引线进行构图以建立与硅化物区域的电接触。 硅化物区域的低接触电阻率提供了通过接触区域传输相对高频电子信号的能力。 在优选的应用中，本发明的方法用于形成用于金属 - 绝缘体 - 半导体场效应晶体管（MISFET）的栅极，源极和漏极的自对准硅化物接触区域。

公开(公告)号：US08528608B2

公开(公告)日：2013-09-10

申请号：US13492477

申请日：2012-06-08

申请人： Rajesh Kelekar ,  Guarav Verma ,  Kurt Weiner

发明人： Rajesh Kelekar ,  Guarav Verma ,  Kurt Weiner

IPC分类号： G01F22/02

CPC分类号： G01F22/02 ,  Y10T137/86035

摘要： A pressure gauge may be coupled to a vessel into which a liquid chemical is to be dispensed. The volume of the vessel may be known and a control device may determine an initial pressure of the vessel using the pressure gauge. A volume of liquid chemical may be dispensed into the vessel which may cause the pressure within the vessel to increase to a second pressure. The control device may determine the second pressure using the pressure gauge may calculate the volume of liquid chemical dispensed into the vessel using the volume of the vessel, the initial pressure of the vessel, and the second pressure of the vessel.

摘要翻译： 压力计可以连接到要分配液体化学品的容器中。 容器的体积可以是已知的，并且控制装置可以使用压力计来确定容器的初始压力。 液体化学品的体积可以分配到容器中，这可能导致容器内的压力增加到第二压力。 控制装置可以使用压力计来确定第二压力可以使用容器的体积，容器的初始压力和容器的第二压力来计算分配到容器中的液体化学品的体积。

公开(公告)号：US08383430B2

公开(公告)日：2013-02-26

申请号：US13399719

申请日：2012-02-17

申请人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

发明人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

IPC分类号： H01L21/00

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US07546573B1

公开(公告)日：2009-06-09

申请号：US11447619

申请日：2006-06-06

申请人： Guarav Verma ,  Rui-Fang Shi

发明人： Guarav Verma ,  Rui-Fang Shi

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： In one embodiment, a computer system a processor and a memory module comprising logic instructions stored on a computer readable medium which. When executed, the logic instructions configure a processor to create a reticle pattern for use in a lithography process, apply an orthogonalization process to the reticle pattern to create an orthogonalized reticle pattern, and use the orthogonalized reticle pattern in an optical proximity correction process.

摘要翻译： 在一个实施例中，计算机系统处理器和存储器模块包括存储在计算机可读介质上的逻辑指令。 当执行时，逻辑指令配置处理器以创建用于光刻工艺的掩模版图案，对光栅图案应用正交化处理以创建正交化的掩模版图案，并在光学邻近校正处理中使用正交化的掩模版图案。