公开(公告)号：US08386210B2

公开(公告)日：2013-02-26

申请号：US13274621

申请日：2011-10-17

Applicant: Prashant B. Phatak

Inventor： Prashant B. Phatak

IPC: G06F19/00

CPC classification number: G05B19/41865 ,  G05B2219/32015 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.

公开(公告)号：US08344375B2

公开(公告)日：2013-01-01

申请号：US13312061

申请日：2011-12-06

Applicant: Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

Inventor： Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

IPC: H01L29/12 ,  H01L29/02

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US20120074376A1

公开(公告)日：2012-03-29

申请号：US13312061

申请日：2011-12-06

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L47/00

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US08097878B2

公开(公告)日：2012-01-17

申请号：US11714326

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L29/12 ,  H01L29/02

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US08716115B2

公开(公告)日：2014-05-06

申请号：US13275822

申请日：2011-10-18

Applicant: Venkat Ananthan ,  Prashant B. Phatak

Inventor： Venkat Ananthan ,  Prashant B. Phatak

IPC: H01L27/32

CPC classification number: H01L27/3295 ,  C23C14/042 ,  H01L22/34 ,  H01L28/60 ,  H01L29/94

Abstract: Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.

Abstract translation: 双荫罩设计可以克服荫罩的尺寸和分辨率限制，为电容器结构提供小的有效面积。 电容器结构具有使用荫罩图案化的底部和顶部电极层，夹持电介质层。 电容器的有效面积是顶部和底部电极的重叠区域，从而允许小面积尺寸而不受电极的尺寸限制。 双荫罩设计可以与高生产率组合工艺结合使用，用于筛选和优化电介质材料和制造工艺。

公开(公告)号：US07629198B2

公开(公告)日：2009-12-08

申请号：US11714334

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L21/00 ,  H01L21/16

CPC classification number: H01L45/04 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US06852649B1

公开(公告)日：2005-02-08

申请号：US09823839

申请日：2001-03-30

Applicant: Prashant B. Phatak ,  Frederick G. Eisenmann, III ,  Michal Fastow

Inventor： Prashant B. Phatak ,  Frederick G. Eisenmann, III ,  Michal Fastow

IPC: H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02274 ,  H01L21/02129 ,  H01L21/31625

Abstract: A method of forming an essentially uniform doped insulating layer is disclosed. Variations in a substrate temperature that may result in a dopant gradient within a doped insulating layer can be compensated for by varying a dopant supply rate in a deposition process. One particular embodiment discloses a method of forming a high density plasma phosphosilicate glass having a phosphorous concentration of 8% or greater by weight that varies by no more than about 1% by weight throughout.

Abstract translation: 公开了一种形成基本均匀的掺杂绝缘层的方法。 可以通过改变沉积工艺中的掺杂剂供应速率来补偿可能导致掺杂绝缘层内的掺杂剂梯度的衬底温度的变化。 一个具体的实施方案公开了一种形成磷酸浓度为8重量％或更高的高密度等离子体磷硅酸盐玻璃的方法，其总重量不超过约1重量％。

公开(公告)号：US08369131B2

公开(公告)日：2013-02-05

申请号：US13286472

申请日：2011-11-01

Applicant: Yun Wang ,  Prashant B Phatak ,  Tony Chiang

Inventor： Yun Wang ,  Prashant B Phatak ,  Tony Chiang

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

公开(公告)号：US08294219B2

公开(公告)日：2012-10-23

申请号：US12179538

申请日：2008-07-24

Applicant: Sandra G. Malhotra ,  Pragati Kumar ,  Sean Barstow ,  Tony Chiang ,  Prashant B. Phatak ,  Wen Wu ,  Sunil Shanker

Inventor： Sandra G. Malhotra ,  Pragati Kumar ,  Sean Barstow ,  Tony Chiang ,  Prashant B. Phatak ,  Wen Wu ,  Sunil Shanker

IPC: H01L21/02

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：US08383430B2

公开(公告)日：2013-02-26

申请号：US13399719

申请日：2012-02-17

Applicant: Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。