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    Image security method and display method of portable terminal
    3.
    发明授权
    Image security method and display method of portable terminal 有权
    便携式终端的图像安全方法和显示方法

    公开(公告)号：US08238878B2

    公开(公告)日：2012-08-07

    申请号：US12617888

    申请日：2009-11-13

    申请人： Sang-Eun Kang ,  Young-Keun Choi

    发明人： Sang-Eun Kang ,  Young-Keun Choi

    IPC分类号： H04M1/66

    CPC分类号： H04M1/72522 ,  H04M1/2745 ,  H04M2250/52 ,  H04N1/00307 ,  H04N1/32128 ,  H04N1/44 ,  H04N1/444 ,  H04N2201/0084 ,  H04N2201/3205

    摘要： An image security method and display method of a portable terminal are provided. The image security method includes photographing an image through a camera, storing the image, and storing Subscriber Identity Module (SIM) information of the portable terminal in EXchangeable Image File (EXIF) information of the image. The image display play method includes executing an image view, comparing Subscriber Identity Module (SIM) information of the portable terminal with SIM information within EXchangeable Image File (EXIF) information of an image stored in the portable terminal, and displaying an image depending on the comparison result.

    摘要翻译： 提供了便携式终端的图像安全方法和显示方法。 图像安全方法包括通过照相机拍摄图像，存储图像，以及将便携式终端的用户识别模块（SIM）信息存储在图像的可替换图像文件（EXIF）信息中。 图像显示播放方法包括执行图像视图，将便携式终端的用户识别模块（SIM）信息与存储在便携式终端中的图像的可替换图像文件（EXIF）信息内的SIM信息进行比较，并且根据 比较结果。

    Reference voltage generating circuit having a power conserving start-up circuit
    4.
    发明授权
    Reference voltage generating circuit having a power conserving start-up circuit 失效
    具有省电启动电路的基准电压发生电路

    公开(公告)号：US5565811A

    公开(公告)日：1996-10-15

    申请号：US388074

    申请日：1995-02-14

    申请人： Jong-Hoon Park ,  Young-Keun Choi

    发明人： Jong-Hoon Park ,  Young-Keun Choi

    IPC分类号： G05F3/24 ,  G11C11/407 ,  G05F3/02

    CPC分类号： G05F3/247

    摘要： A power conserving circuit is disclosed which has a start-up circuit for initiating operation of a reference voltage generator. Included are a sensing circuit for producing a pulse signal in response to initial application of an external power source; a reference voltage generator for producing a constant reference voltage independent from an external power source voltage; and a start-up circuit for starting operation of the reference voltage generator during an interval of a pulse produced by the sensing circuit. The start-up circuit includes a switch for connecting and disconnecting the external power source to the reference voltage output port, and a voltage reducing element connected between the switch and the reference voltage output port.

    摘要翻译： 公开了一种省电电路，其具有用于启动参考电压发生器的操作的启动电路。 包括响应于外部电源的初始应用产生脉冲信号的感测电路; 用于产生与外部电源电压无关的恒定参考电压的参考电压发生器; 以及用于在由感测电路产生的脉冲的间隔期间开始参考电压发生器的操作的启动电路。 启动电路包括用于将外部电源连接到参考电压输出端口的开关，以及连接在开关和参考电压输出端口之间的降压元件。

    Burn-in test circuit for semiconductor memory device
    5.
    发明授权
    Burn-in test circuit for semiconductor memory device 失效
    半导体存储器件的老化测试电路

    公开(公告)号：US5452253A

    公开(公告)日：1995-09-19

    申请号：US125574

    申请日：1993-09-23

    申请人： Young-Keun Choi

    发明人： Young-Keun Choi

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  G11C29/14 ,  G11C29/46 ,  G11C29/50

    CPC分类号： G11C29/46 ,  G11C29/50

    摘要： For enabling burn-in test in a memory device such that a test mode timing signal and detected voltage level of an external power supply are combined in order to maintain compatibility with conventional timing signals, and for preventing the burn-in test circuit from dissipating power in a standby state, there is provided a sense control circuit for producing a short duration enable pulse in response to an input level of timing signals such as WCBR, CBR, or ROR, and a voltage sensor for sensing the input voltage level of the external power supply voltage during the short duration pulse. Also, the circuit includes a burn-in sensor which generates a signal output which determines set or reset of the burn-in test mode in response to the timing signals and the detected level of the voltage sensor. Since the voltage sensor is operated only when the short duration pulse is applied, the power consumption in the voltage sensor is negligible even during the sensing operation of the external supply voltage. Further, the burn-in test mode is activated in the memory device if the external input signals satisfy the particular condition and the level of the external supply voltage is higher than the preset burn-in test voltage, thereby the memory device is prevented from entering into the burn-in test mode due to noise of the external power supply voltage.

    摘要翻译： 为了在存储器件中实现老化测试，使得测试模式定时信号和外部电源的检测电压电平相结合，以便保持与常规定时信号的兼容性，并且防止老化测试电路消耗功率 在待机状态下，提供了用于响应于诸如WCBR，CBR或ROR的定时信号的输入电平产生短持续时间使能脉冲的感测控制电路，以及用于感测外部的输入电压电平的电压传感器 在短脉冲期间的电源电压。 此外，电路包括老化传感器，其产生响应于定时信号和检测到的电压传感器的电平而确定老化测试模式的设置或复位的信号输出。 由于电压传感器仅在施加短持续脉冲时才起作用，因此即使在外部电源电压的感测操作期间，电压传感器的功耗也可忽略不计。 此外，如果外部输入信号满足特定条件并且外部电源电压的电平高于预设的老化测试电压，则在存储器件中激活老化测试模式，从而防止存储器件进入 由于外部电源电压的噪声，进入老化测试模式。

    Burn-in voltage detection circuit for semiconductor chip
    6.
    发明授权
    Burn-in voltage detection circuit for semiconductor chip 失效
    半导体芯片的老化电压检测电路

    公开(公告)号：US5656944A

    公开(公告)日：1997-08-12

    申请号：US559700

    申请日：1995-11-15

    申请人： Young-Keun Choi

    发明人： Young-Keun Choi

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/06 ,  G11C29/56 ,  H01L21/66

    CPC分类号： G01R31/2855

    摘要： An improved burn-in voltage detection circuit for a semiconductor chip capable of detecting a predetermined voltage level related to a burn-in operation using a specific element irrespective of manufacturing variation, which includes an external voltage detection circuit for detecting whether an external voltage level is higher than a prescribed internal reference voltage level, and in response producing a burn-in enable signal; and a burn-in conversion detection circuit including a hysteresis characteristic, activated by the burn-in enable signal and responsive to the externally applied voltage and the internal reference voltage, for producing a burn-in signal of a first state as the external voltage is increased in magnitude above the level of the prescribed internal reference voltage by a component of the hysteresis characteristic, and a burn-in signal of a second state as the external voltage is reduced in magnitude below the level of the prescribed internal reference voltage by a component of the hysteresis characteristic.

    摘要翻译： 一种用于半导体芯片的改进的老化电压检测电路，其能够检测与使用特定元件的老化操作相关的预定电压电平，而不管制造变化，其包括外部电压检测电路，用于检测外部电压电平是否为 高于规定的内部参考电压电平，并且响应产生老化使能信号; 以及老化转换检测电路，其包括通过所述老化使能信号而激活的响应于所述外部施加的电压和所述内部参考电压的滞后特性，用于产生作为外部电压的第一状态的老化信号 通过滞后特性的分量，在规定的内部基准电压的电平以上的范围内增加幅度，并且当外部电压的幅度比规定的内部参考电压的电平低的程度降低时，第二状态的老化信号被组件 的滞后特性。