公开(公告)号：US20230195986A1

公开(公告)日：2023-06-22

申请号：US18010131

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Kai WANG ,  Tai YANG ,  Wei BAO

IPC: G06F30/367 ,  G06N3/0442 ,  G06N3/045 ,  G06N3/0464

CPC classification number: G06F30/367 ,  G06N3/0442 ,  G06N3/045 ,  G06N3/0464 ,  G06F2119/12

Abstract: Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

公开(公告)号：US20230153502A1

公开(公告)日：2023-05-18

申请号：US16969474

申请日：2020-02-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Tai YANG ,  Jingjing GUO

IPC: G06F30/3315 ,  G06F30/3312

CPC classification number: G06F30/3315 ,  G06F30/3312 ,  G06F2119/12

Abstract: It discloses a statistical timing analysis method of an integrated circuit under an advanced process and a low voltage. By simulating the fluctuation of process parameters of the integrated circuit under the advanced process, a statistical circuit timing model is built based on the relationship between the delay of the integrated circuit under the low voltage and the process parameters, and the maximum delay and the minimum delay under timing fluctuation of the integrated circuit are analyzed.

公开(公告)号：US20240265181A1

公开(公告)日：2024-08-08

申请号：US18571727

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Qianqian SONG ,  Kai WANG

IPC: G06F30/337 ,  G06F119/06

CPC classification number: G06F30/337 ,  G06F2119/06

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

公开(公告)号：US20230214567A1

公开(公告)日：2023-07-06

申请号：US18011443

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Jiahao WANG ,  Haiyang JIANG

IPC: G06F30/3315 ,  G06F30/337

CPC classification number: G06F30/3315 ,  G06F30/337 ,  G06F2119/12

Abstract: Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

公开(公告)号：US20230195985A1

公开(公告)日：2023-06-22

申请号：US18014002

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Haiyang JIANG ,  Jiahao WANG

IPC: G06F30/3312 ,  G06F30/3315

CPC classification number: G06F30/3312 ,  G06F30/3315 ,  G06F2119/12

Abstract: Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

公开(公告)号：US20210056468A1

公开(公告)日：2021-02-25

申请号：US17043715

申请日：2019-03-12

Applicant: Southeast University

Inventor： Peng CAO ,  Bingqian XU ,  Jingjing GUO ,  Mengxiao LI ,  Jun YANG

IPC: G06N20/00 ,  G01R31/28

Abstract: A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.

公开(公告)号：US20240273272A1

公开(公告)日：2024-08-15

申请号：US18571739

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Guoqing HE ,  Tai YANG

IPC: G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

公开(公告)号：US20240265190A1

公开(公告)日：2024-08-08

申请号：US18567044

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Xu CHENG ,  Tai YANG

IPC: G06F30/3953

CPC classification number: G06F30/398 ,  G06F30/27 ,  G06F30/33 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/392 ,  G06F30/3953

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

公开(公告)号：US20230153501A1

公开(公告)日：2023-05-18

申请号：US17796794

申请日：2022-03-10

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Bingqian XU ,  Haiyang JIANG ,  Qianqian SONG

IPC: G06F30/3312

CPC classification number: G06F30/3312 ,  G06F2119/12

Abstract: Disclosed is a near-threshold cell circuit delay model, where obtaining parameters includes obtaining process parameters, current parameters and delay parameters with slow input transition; judging a cell circuit type includes judging whether a cell circuit is an inverter, a stacked structure cell or a parallel structure cell, calculating currents and a current integral according to the cell circuit type, calculating a mean value, a variance and a skewness of a logarithm of the current sum, and calculating a mean value and a variance of an equivalent threshold voltage; judging a delay type includes calculating an overshoot time and a delay according to the cell circuit type, comparing the magnitude relationship among an input transition time, the overshoot time and the delay, and judging whether the delay type is ultra-fast input, fast input or slow input; establishing a cell circuit nominal delay model is establishing the cell circuit nominal delay model according to the cell circuit type and the delay type, and obtaining a nominal delay value; and establishing a cell circuit statistical delay model is establishing the cell circuit statistical delay model according to the cell circuit type and the delay type.