公开(公告)号：US10770510B2

公开(公告)日：2020-09-08

申请号：US15865135

申请日：2018-01-08

申请人： SPIN MEMORY, INC.

发明人： Gian Sharma ,  Amitay Levi ,  Kuk-Hwan Kim

IPC分类号： H01L27/22 ,  H01L29/78 ,  H01L43/02 ,  H01L29/06

摘要： A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

公开(公告)号：US10658425B2

公开(公告)日：2020-05-19

申请号：US16237143

申请日：2018-12-31

申请人： Spin Memory, Inc.

发明人： Kuk-Hwan Kim ,  Dafna Beery ,  Amitay Levi ,  Andrew J. Walker

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L29/66 ,  H01L29/78 ,  H01L43/10 ,  H01L43/12

摘要： A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

公开(公告)号：US10438999B2

公开(公告)日：2019-10-08

申请号：US15859245

申请日：2017-12-29

申请人： Spin Memory, Inc.

发明人： Gian Sharma ,  Amitay Levi ,  Andrew J. Walker ,  Kuk-Hwan Kim ,  Dafna Beery

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

摘要： A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.

公开(公告)号：US20190214432A1

公开(公告)日：2019-07-11

申请号：US15866381

申请日：2018-01-09

申请人： Spin Memory, Inc.

发明人： Kuk-Hwan Kim ,  Marcin Gajek ,  Dafna Beery ,  Amitay Levi

IPC分类号： H01L27/22 ,  H01L29/66 ,  H01L29/78 ,  H01L43/02 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L29/66666 ,  H01L29/7727 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/12

摘要： According to one embodiment, a method includes forming a drain contact above a channel, each having a hollow circular cross-section thereof along a plane perpendicular to a film thickness direction, forming gate dielectric layers on sides of the drain contact and the channel, forming a source line positioned below the channel that is electrically coupled to a plurality of channels in a direction along the plane, forming gate layers on sides of the gate dielectric layers, where an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane, and where an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane, forming an electrode above the upper surface of the drain contact, and forming a fourth insulative layer on sides of the electrode along the plane.

公开(公告)号：US10347822B1

公开(公告)日：2019-07-09

申请号：US15857358

申请日：2017-12-28

申请人： Spin Memory, Inc.

发明人： Gian Sharma ,  Amitay Levi ,  Andrew J. Walker ,  Kuk-Hwan Kim ,  Dafna Beery

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/12

摘要： A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.

公开(公告)号：US10347311B1

公开(公告)日：2019-07-09

申请号：US15857430

申请日：2017-12-28

申请人： Spin Memory, Inc.

发明人： Gian Sharma ,  Amitay Levi ,  Andrew J. Walker ,  Kuk-Hwan Kim ,  Dafna Beery

IPC分类号： H01L29/66 ,  G11C11/16 ,  H01L29/78 ,  H01L27/22

摘要： A switching device, according to one embodiment, includes: a cylindrical pillar; an annular cylindrical oxide layer which encircles a portion of the cylindrical pillar; an annular cylindrical gate contact which encircles a portion of the annular cylindrical oxide layer; and a source contact which encircles a portion of the cylindrical pillar toward a first end of the cylindrical pillar. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved cylindrical gate contacts, improved source contacts, and/or improved drain contacts. These improved systems and components thereof may be implemented in vertical transistor structures which also include the aforementioned cylindrical pillar and cylindrical gate contact in comparison to conventional surface transistor structures.

公开(公告)号：US20190206937A1

公开(公告)日：2019-07-04

申请号：US15859222

申请日：2017-12-29

申请人： Spin Memory, Inc.

发明人： Gian Sharma ,  Amitay Levi ,  Andrew J. Walker ,  Kuk-Hwan Kim ,  Dafna Beery

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/228 ,  H01L29/66666 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab. Moreover, other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the annular cylindrical channels, the source contact tabs, and/or the cylindrical pillar gate contacts for vertical transistor structures in comparison to conventional surface transistor structures.

公开(公告)号：US20190206932A1

公开(公告)日：2019-07-04

申请号：US15859070

申请日：2017-12-29

申请人： Spin Memory, Inc.

发明人： Kuk-Hwan Kim ,  Dafna Beery ,  Amitay Levi ,  Andrew J. Walker

IPC分类号： H01L27/22 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： According to one embodiment, a method of forming a magnetic memory device includes forming a source region including a first semiconductor material having a first conductivity above a substrate, forming an array of three-dimensional (3D) structures above the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each 3D structure, forming a first isolation region in the cavity region above the substrate, forming a first gate region above the first isolation region in the cavity region, and forming a second isolation region above the first gate region, wherein a nth gate region is formed above a (n+1) isolation region thereafter until a top of the array of 3D structures, wherein each nth gate region is coupled to each nth perpendicular magnetic tunnel junction sensor of each 3D structure.

公开(公告)号：US20210305256A1

公开(公告)日：2021-09-30

申请号：US16828879

申请日：2020-03-24

申请人： Spin Memory, Inc.

发明人： Andrew J. Walker ,  Dafna Beery ,  Peter Cuevas ,  Amitay Levi

IPC分类号： H01L27/108 ,  H01L29/45 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065

摘要： A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

公开(公告)号：US10916582B2

公开(公告)日：2021-02-09

申请号：US15859453

申请日：2017-12-30

申请人： Spin Memory, Inc.

发明人： Kuk-Hwan Kim ,  Dafna Beery ,  Amitay Levi ,  Andrew J. Walker

IPC分类号： H01L27/22 ,  H01L21/28 ,  H01L29/417 ,  H01L21/768 ,  H01L43/12 ,  H01L23/528 ,  G11C11/16 ,  H01L23/522 ,  H01L43/02 ,  H01L43/08 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/423 ,  H01F10/32 ,  H01L29/66 ,  H01L23/532

摘要： According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.