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1.发明授权公开(公告)号：US07235502B2
公开(公告)日：2007-06-26
申请号：US11096515
申请日：2005-03-31
IPC分类号： H01L21/31
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译： 栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。 然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。 氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。 高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。 形成过渡电介质膜（205）可以包括形成多个过渡介电层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。 形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。
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公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。
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公开(公告)号：US06686282B1
公开(公告)日：2004-02-03
申请号：US10403967
申请日：2003-03-31
IPC分类号： H01L2144
CPC分类号： H01L21/823842 , H01L21/28079
摘要： Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.
摘要翻译： 使用电镀，N沟道和P沟道晶体管的金属栅极由不同的材料形成，以实现这些N和P沟道晶体管的适当的功函数。 用与期望层的生长一致的种子层实现电镀。 优选的材料选自包含钌，氧化钌，铱，钯，铂，镍，锇和钴的铂金属。 这些是有吸引力的金属，因为它们具有相对高的导电性，可以被电镀，并且提供了用于形成P和N沟道晶体管的工作功能的良好选择。
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公开(公告)号：US07704821B2
公开(公告)日：2010-04-27
申请号：US11146826
申请日：2005-06-07
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
摘要翻译： 用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。 形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。 沉积介电堆叠包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。 沉积一个电介质层包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。 沉积多个子层包括沉积无氮的子层并沉积含氮的子层。 沉积无氮子层包括用HfCl 4脉冲ALD室，用惰性气体冲洗室，用H 2 O或D 2 O脉冲室，并用惰性气体清洗室。
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公开(公告)号：US06902969B2
公开(公告)日：2005-06-07
申请号：US10632473
申请日：2003-07-31
申请人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
发明人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。 栅极电介质或蚀刻停止件可以与衬底接触。 蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。
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公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译： 用氮化步骤和退火处理栅极电介质。 之后，进行另外的氮化步骤和退火。 第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。
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公开(公告)号：US07144825B2
公开(公告)日：2006-12-05
申请号：US10687271
申请日：2003-10-16
IPC分类号： H01L21/00
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.
摘要翻译： 公开了形成电介质的方法。 该方法包括在半导体材料上形成第一介电层。 扩散阻挡材料被引入到第一介电层中。 最后，在引入之后，在第一电介质层上形成第二电介质层。
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8.发明授权公开(公告)号：US07015153B1
公开(公告)日：2006-03-21
申请号：US10969634
申请日：2004-10-20
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
IPC分类号： H01L21/31
CPC分类号： C23C14/0057 , C23C16/30 , C23C16/45527 , H01L21/28229 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.
摘要翻译： 一种用于形成半导体器件的至少一部分的方法包括提供半导体衬底，使第一前体气体流过衬底以形成覆盖半导体衬底的第一含金属层，并且在完成所述第一前体气体流动步骤 使第一含氘吹扫气体流过第一含金属层，将氘掺入第一含金属层并且还吹扫第一前体气体。 该方法还可以包括使第二前体气体流过第一含金属层以与第一含金属层反应以形成含金属化合物的层，并将第二含氘的净化气体流过含金属化合物的层 层将氘并入含金属化合物的层中并且还吹扫第二前体气体。
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公开(公告)号：US07288458B2
公开(公告)日：2007-10-30
申请号：US11302770
申请日：2005-12-14
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
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10.发明授权Dual metal gate electrode semiconductor fabrication process and structure thereof 失效双金属栅电极半导体制造工艺及其结构公开(公告)号：US07074664B1
公开(公告)日：2006-07-11
申请号：US11092418
申请日：2005-03-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
摘要翻译： 半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。 第二栅极电极层形成在第一栅极电极层和栅极电介质上。 去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。 可以形成第三栅极电极层，覆盖第一和第二栅电极层。 第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。 去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。
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