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公开(公告)号：US5602838A
公开(公告)日：1997-02-11
申请号：US360518
申请日：1994-12-21
CPC分类号： H04B7/18521
摘要： A global satellite communication network is described. The global satellite communication network comprises a plurality of polar communication loops and a plurality of longitudinal communication loops. The polar and longitudinal communication loops are formed in three dimensional space. Each polar communication loop includes a plurality of nodes each bidirectionally communicating with adjacent communicating nodes in the polar communication loops. Each longitudinal communication loop includes a plurality of nodes each bidirectionally communicating with adjacent communicating nodes in the longitudinal communication loops. Each longitudinal communication loop is in communication with each polar communication loop via a node which is common to both the longitudinal communication loop and the polar communication loop. The common node includes a switch to transfer packets received from the polar communication loop to the longitudinal communication loop, and vice versa, as a function of destination addresses contained in the packets.
摘要翻译： 描述了一个全球卫星通信网络。 全球卫星通信网络包括多个极性通信环路和多个纵向通信环路。 极地和纵向连通环形成三维空间。 每个极性通信环路包括多个节点，每个节点与极地通信环路中的相邻通信节点双向通信。 每个纵向通信环路包括与纵向通信环路中的相邻通信节点双向通信的多个节点。 每个纵向通信环路经由通过纵向通信环路和极性通信环路共同的节点与每个极性通信环路通信。 公共节点包括将从极性通信环路接收的分组传送到纵向通信环路的开关，反之亦然，作为分组中包含的目的地地址的函数。
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公开(公告)号：US5383180A
公开(公告)日：1995-01-17
申请号：US65001
申请日：1993-05-24
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04 , H04Q2213/13106 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/13385 , H04Q2213/13393
摘要： Disclosed is a circuit which allows a digital loop carrier remote terminal to communicate with a local digital switch having a TR8 interface. The circuit includes a pair of microprocessors and time slot interchangers which multiplex, demultiplex and distribute the data fields associated with the interface.
摘要翻译： 公开了允许数字环路载波远程终端与具有TR8接口的本地数字交换机进行通信的电路。 该电路包括一对微处理器和时隙互换器，其对与该接口相关联的数据字段进行复用，解复用和分配。
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3.发明授权Apparatus and method for temperature-compensating diffraction-based optical devices 有权用于温度补偿衍射的光学器件的装置和方法公开(公告)号：US06498681B2
公开(公告)日：2002-12-24
申请号：US09848135
申请日：2001-05-03
IPC分类号： G02B2744
CPC分类号： G02B6/29314 , G02B5/18 , G02B6/29398 , G02B26/0808 , G02B27/108 , G02B27/1086
摘要： A temperature-compensated optical grating is fed an optical probe signal of a predetermined wavelength. An optical detector having a plurality of apertures for receiving an optical signal is positioned to detect a probe light signal from the grating and to detect the deflection of the probe light signal from a preferred location. The detector provides an indication of the deflection to a controller which operates a temperature adjustment device, such as a fan or thermoelectric cooler to adjust the temperature of the grating in a direction which reduces the deflection.
摘要翻译： 温度补偿光栅被馈送预定波长的光探针信号。 具有用于接收光信号的多个孔的光学检测器被定位成检测来自光栅的探测光信号并且检测来自优选位置的探测光信号的偏转。 检测器提供对控制器的偏转的指示，该控制器操作诸如风扇或热电冷却器的温度调节装置，以在减小偏转的方向上调节光栅的温度。
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公开(公告)号：US06266333B1
公开(公告)日：2001-07-24
申请号：US09089009
申请日：1998-06-02
IPC分类号： H04L1228
CPC分类号： H04L45/10 , H04L49/606 , H04L2012/5665 , H04Q3/52 , H04Q11/0478 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13196 , H04Q2213/1329 , Y10S370/907
摘要： Data signals from two or more different communication networks conforming to one or more different transmission protocols are re-formatted into an internal data format for purposes of routing the data signals. The internal format has one or more fields corresponding to terminated overhead data for storing payload data. In one embodiment, a switching system has a network-independent switch and two or more network-dependent port units. Each port unit is configured to interface with a different communication network and to convert data signals between the transmission protocol of the corresponding communication network and the internal format. The switch receives and routes the data signals in the internal format and transmits the routed data signals back to the appropriate port units for re-formatting for transmission to the corresponding communication networks. The switching system can be configured as the interface between two or more different communication networks, including synchronous networks such as SONET networks and asynchronous network such as ATM and LAN networks.
摘要翻译： 为了路由数据信号的目的，将符合一个或多个不同传输协议的两个或多个不同通信网络的数据信号重新格式化为内部数据格式。 内部格式具有一个或多个对应于用于存储有效负载数据的终止开销数据的字段。 在一个实施例中，交换系统具有网络独立的交换机和两个或多个基于网络的端口单元。 每个端口单元被配置为与不同的通信网络接口并且在相应通信网络的传输协议和内部格式之间转换数据信号。 交换机以内部格式接收和路由数据信号，并将路由的数据信号发送回适当的端口单元，以进行重新格式化，以传输到相应的通信网络。 交换系统可以被配置为两个或多个不同通信网络之间的接口，包括诸如SONET网络的同步网络和诸如ATM和LAN网络的异步网络。
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公开(公告)号：US5606551A
公开(公告)日：1997-02-25
申请号：US360517
申请日：1994-12-21
CPC分类号： H04L45/06 , H04L12/2852 , H04L12/4637
摘要： A communication network called a bidirectional mesh network (MSN), also called bi-MSN, is described. The bi-MSN includes a plurality of first communication loops (horizontal loops) each comprising a plurality of nodes interconnected to one another by bidirectional communication links. The bi-MSN also includes a plurality of second communication loops (vertical loops) each comprising a plurality of nodes interconnected to one another by bidirectional communication links. Each second communication loop is connected to each first communication loop at a node which is common to both the second communication loop and the first communication loop. This common node (and, in fact, each node in the bi-MSN) includes a switch to transfer packets from the first communication loop to the second communication loop, and vice versa, as a function of destination addresses contained in the packets.
摘要翻译： 描述了称为双向网状网络（MSN）的通信网络，也称为双MSN。 双MSN包括多个第一通信环路（水平环路），每个通信环路包括通过双向通信链路彼此互连的多个节点。 双MSN还包括多个第二通信环（垂直环），每个第二通信环包括通过双向通信链路彼此互连的多个节点。 每个第二通信环路在与第二通信环路和第一通信环路共同的节点处连接到每个第一通信环路。 这个公共节点（实际上是双MSN中的每个节点）包括将分组从第一通信环路传送到第二通信环路的交换机，反之亦然，作为分组中包含的目的地地址的功能。
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公开(公告)号：US07149661B1
公开(公告)日：2006-12-12
申请号：US10859672
申请日：2004-06-03
IPC分类号： G01N21/00
CPC分类号： H04L1/203
摘要： A method for determining a quality indication, such as a bit error rate or a signal to noise ratio, of a photonic signal is described. The photonic signal is sampled, and then an estimated quality indication, such as the bit error rate, is calculated utilizing statisical analysis of the sampled photonic signal.
摘要翻译： 描述了用于确定光子信号的质量指示（诸如误码率或信噪比）的方法。 对光子信号进行采样，然后利用采样的光子信号的统计分析来计算估计的质量指示，例如误码率。
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公开(公告)号：US07813899B2
公开(公告)日：2010-10-12
申请号：US11603700
申请日：2006-11-21
IPC分类号： G01B9/02
CPC分类号： H04L1/203
摘要： A method for determining a quality indication, such as a bit error rate or a signal to noise ratio, of a photonic signal is described. The photonic signal is sampled, and then an estimated quality indication, such as the bit error rate, is calculated utilizing statisical analysis of the sampled photonic signal.
摘要翻译： 描述了用于确定光子信号的质量指示（诸如误码率或信噪比）的方法。 对光子信号进行采样，然后利用采样的光子信号的统计分析来计算估计的质量指示，例如误码率。
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公开(公告)号：US06617566B2
公开(公告)日：2003-09-09
申请号：US09848134
申请日：2001-05-03
IPC分类号： H01J4014
CPC分类号： G06K7/10851
摘要： An optical pattern detector in accordance with the principles of the present invention includes an optical sensor configured to sense a plurality of optical signals, an optical summer configured to receive and sum the sensed optical signals, and a sampler configured to sample the summed optical signals. The pattern detector may be configured to receive serial or parallel binary optical signals and, with various weightings of the sensed optical signals, may operate as an optical digital to analog converter, automatically decoding binary digital optical signals.
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9.发明授权Ram-based associative content-addressable memory device, method of operation thereof and ATM communication switching system employing the same 失效基于Ram的关联内容可寻址存储器件，其操作方法和采用该存储器件的ATM通信交换系统
公开(公告)号：US6097724A
公开(公告)日：2000-08-01
申请号：US911646
申请日：1997-08-15
CPC分类号： H04L49/309 , G11C15/00 , H04L45/7453 , H04Q11/0478
摘要： A memory device, a method of content-addressing a memory device to validate an incoming pattern and an Asynchronous Transfer Mode (ATM) communication switching system incorporating the device or the method. In one embodiment, the device includes: (1) a validation random access memory (RAM) having a plurality of addressable locations therein, the addressable locations containing validation indicators corresponding to patterns that have been programed into the validation RAM and (2) circuitry, coupled to the validation RAM, that provides an incoming pattern to the validation RAM and retrieves a corresponding validation indicator from the validation RAM, the validation indicator indicating whether the incoming pattern had been programed into the validation RAM. The memory device thereby functions as a content-addressable memory (CAM).
摘要翻译： 一种存储器件，一种内存寻址存储器件以验证输入模式的方法以及结合该器件或该方法的异步传输模式（ATM）通信交换系统。 在一个实施例中，设备包括：（1）其中具有多个可寻址位置的验证随机存取存储器（RAM），可寻址位置包含对应于已被编程到验证RAM中的模式的验证指示符，以及（2）电路， 耦合到验证RAM，其向验证RAM提供输入模式并从验证RAM检索相应的验证指示符，该验证指示符指示输入模式是否被编程到验证RAM中。 因此，存储器件用作内容寻址存储器（CAM）。
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公开(公告)号：US5590323A
公开(公告)日：1996-12-31
申请号：US242526
申请日：1994-05-13
CPC分类号： G06F9/4887 , G06F8/451
摘要： A process for producing a parallel processor system having the minimum number of microprocessors necessary execute in real time a set of tasks of a multi-tasking application such that execution of an activity of a first task is followed by execution of an activity of a second task. The process includes the step of selecting an initial number of microprocessors for executing the application in real-time. The selecting step includes placing in a first column of a matrix all real-time constrained tasks specific to the application and associating a row of dependent tasks with each task placed in the first column of the matrix to define a plurality of task subsets, each subset incorporating a maximum number of intradependent tasks and a minimum number of interdependent tasks and the number of subsets corresponding to the initial number of microprocessors. The inventive process further includes the steps of listing dependencies between rows in a second column of the matrix, assigning a priority p.sub.i to each task where p.sub.i is between 0 and 1, subdividing at least one of the tasks into discrete activities, each of the activities having a corresponding execution time t.sub.ij, estimating the execution time for each activity, reducing the number of rows in the matrix by grouping together tasks having activities that can be executed within a predetermined time window T, and providing a number of microprocessors corresponding to the number of rows obtained from the rows reducing step.
摘要翻译： 一种用于产生具有最少数量的微处理器的并行处理器系统的过程，其必需实施多任务应用的一组任务，使得第一任务的活动的执行之后是执行第二任务的活动 。 该过程包括选择用于实时执行应用的初始数量的微处理器的步骤。 所述选择步骤包括将矩阵的第一列放入所述应用特有的所有实时约束任务，并且将一系列从属任务与放置在矩阵的第一列中的每个任务相关联以定义多个任务子集，每个子集 结合最大数量的独立任务和最小数量的相互依赖的任务以及与初始微处理器数量相对应的子集数。 本发明的方法还包括以下步骤：列出矩阵的第二列中的行之间的依赖关系，将pi优先级分配给pi在0和1之间的每个任务，将任务中的至少一个细分为离散活动，每个活动 具有相应的执行时间tij，估计每个活动的执行时间，通过将具有在预定时间窗口T内可执行的活动分组在一起的方式减少矩阵中的行数，以及提供与数字对应的多个微处理器 从行减少步骤获得的行。
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