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76 条记录 (耗时 0.033 秒)

    Method for operating a memory cell array
    1.
    发明授权
    Method for operating a memory cell array 有权
    操作存储单元阵列的方法

    公开(公告)号：US07113428B2

    公开(公告)日：2006-09-26

    申请号：US10954642

    申请日：2004-09-30

    申请人： Stefan Trost ,  Georg Tempel ,  Matthias Ernst ,  Martin Steinbrück

    发明人： Stefan Trost ,  Georg Tempel ,  Matthias Ernst ,  Martin Steinbrück

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/3427

    摘要： Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

    摘要翻译： 在对存储单元阵列的选定闪存单元进行重新编程之前，通过Fowler-Nordheim隧道从电子区域（C）中的存储层（M）中移除的电子，用于存储器单元的初始编程的较低电位是 而相关联的位线（BL m ）保持在基本电位的情况下被施加到相关字线（WL SUB）。 由此实现的是在编程操作期间发生的门扰动不会导致沿着受影响的字线（WL SUB）的不稳定的位。

    Semiconductor component with trench insulation and corresponding production method
    3.
    发明授权
    Semiconductor component with trench insulation and corresponding production method 有权
    具有沟槽绝缘的半导体元件及相应的生产方法

    公开(公告)号：US08552524B2

    公开(公告)日：2013-10-08

    申请号：US10523239

    申请日：2003-07-19

    申请人： Franz Schuler ,  Georg Tempel

    发明人： Franz Schuler ,  Georg Tempel

    IPC分类号： H01L29/00 ,  H01L21/8238

    CPC分类号： H01L21/763 ,  H01L21/76229 ,  H01L21/76232

    摘要： The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation having a deep isolation trench with a covering insulation layer, a side wall insulation layer and an electrically conductive filling layer, which is electrically connected to a predetermined doping region of the semiconductor substrate in a bottom region of the trench. The use of a trench contact, which has a deep contact trench with a side wall insulation layer and an electrically conductive filling layer, which is likewise electrically connected to the predetermined doping region of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

    摘要翻译： 本发明涉及具有沟槽隔离和相关制造方法的半导体部件，具有具有覆盖绝缘层的深隔离沟槽，侧壁绝缘层和导电填充层的沟槽隔离件，其电连接到预定的 在沟槽的底部区域中的半导体衬底的掺杂区域。 与接触沟槽的底部区域同样电连接到半导体衬底的预定掺杂区域的沟槽接触的使用，其具有与侧壁绝缘层和导电填充层的深接触沟槽，使得 可以减小面积要求来改善电屏蔽性能。

    Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement
    4.
    发明申请
    Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement 有权
    非易失性存储器元件及其生产方法和存储器存储器布置

    公开(公告)号：US20110159661A1

    公开(公告)日：2011-06-30

    申请号：US13043129

    申请日：2011-03-08

    申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L21/02

    CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

    摘要翻译： 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

    Discrete Trap Memory (DTM) Mediated by Fullerenes
    6.
    发明申请
    Discrete Trap Memory (DTM) Mediated by Fullerenes 审中-公开
    离散陷阱记忆（DTM）由富勒烯介导

    公开(公告)号：US20080296662A1

    公开(公告)日：2008-12-04

    申请号：US11755509

    申请日：2007-05-30

    申请人： Gerhard Poeppel ,  Georg Tempel

    发明人： Gerhard Poeppel ,  Georg Tempel

    IPC分类号： H01L29/792 ,  H01L21/3205

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2216/06 ,  Y10S977/763 ,  Y10S977/773

    摘要： A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

    摘要翻译： 一种分立陷阱存储器，包括硅衬底层，硅衬底层上的底部氧化物层，底部氧化物层上的富勒烯层，富勒烯层上的顶部氧化物层和顶部氧化物层上的栅极层; 其中富勒烯层包含作为电荷阱的球形，椭圆形或内面的富勒烯。

    Non-volatile semiconductor memory element and corresponding production and operation method
    7.
    发明申请
    Non-volatile semiconductor memory element and corresponding production and operation method 有权
    非易失性半导体存储器元件及相应的生产和操作方法

    公开(公告)号：US20060226466A1

    公开(公告)日：2006-10-12

    申请号：US10524158

    申请日：2003-08-08

    申请人： Franz Schuler ,  Georg Tempel

    发明人： Franz Schuler ,  Georg Tempel

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66833 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/7923

    摘要： The invention relates to a nonvolatile semiconductor storage element and an associated production and control method, comprising a semiconductor substrate (1) in which a source region (S), a drain region (D) and an intermediate channel region are formed. On a first part section (I) of the channel region, a control layer (5) is formed and insulated from the channel region by a first insulating layer (2A) whereas respective charge storage layers (3A and 3B) are formed in a second part section (IIA, IIB) of the channel region and are insulated from the channel region by a second insulating layer (2BA and 2BB). On the charge storage layer (3A, 3B), a programming layer (6A, 6B) is formed and insulated from that by a third insulating layer (4A, 4B) and is electrically connected to a respective source region (S) and drain region (D) via a respective interconnect layer (6AA, 6BB).

    摘要翻译： 本发明涉及一种非易失性半导体存储元件及相关的制造和控制方法，包括其中形成源极区（S），漏极区（D）和中间沟道区的半导体衬底（1）。 在沟道区的第一部分（I）上，通过第一绝缘层（2A）形成控制层（5）并与沟道区绝缘，而形成各自的电荷存储层（3A和3B） 在沟道区域的第二部分部分（IIA，IIB）中，并且通过第二绝缘层（2 BA和2BB）与沟道区域绝缘。 在电荷存储层（3A，3B）上，编程层（6A，6B）与第三绝缘层（4A，4B）的编程层（6A，6B）形成绝缘，并与第一绝缘层 （6A，6BB）中的至少一个（S）和漏极区（D）。

    Bit line structure and production method thereof
    8.
    发明申请
    Bit line structure and production method thereof 有权
    位线结构及其制造方法

    公开(公告)号：US20060131637A1

    公开(公告)日：2006-06-22

    申请号：US11273668

    申请日：2005-11-14

    申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

    摘要翻译： 本公开涉及位线结构和相关联的位线结构的制造方法。 在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。 隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

    Bit line structure and method for the production thereof
    9.
    发明申请
    Bit line structure and method for the production thereof 有权
    位线结构及其制造方法

    公开(公告)号：US20060108692A1

    公开(公告)日：2006-05-25

    申请号：US11273595

    申请日：2005-11-14

    申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L23/52

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

    摘要翻译： 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

    Non-volatile memory element and production method thereof and storage memory arrangement
    10.
    发明申请
    Non-volatile memory element and production method thereof and storage memory arrangement 有权
    非易失性存储元件及其制造方法和存储存储器装置

    公开(公告)号：US20060097238A1

    公开(公告)日：2006-05-11

    申请号：US10522386

    申请日：2003-07-19

    申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： A nonvolatile memory element and to associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

    摘要翻译： 提出了一种非易失性存储器元件以及相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。