Frame classification using classification keys
    1.
    发明授权
    Frame classification using classification keys 失效
    使用分类键进行帧分类

    公开(公告)号:US5748905A

    公开(公告)日:1998-05-05

    申请号:US701335

    申请日:1996-08-30

    IPC分类号: H04L29/06 G06F13/00

    CPC分类号: H04L29/06 H04L69/22

    摘要: An improved method and apparatus for recognizing, classifying and processing frames received at a frame processor in a computer network is disclosed. Following receipt of a frame at an input port of a frame processor, source and destination addresses are parsed from the frame. A plurality of lookup tables are provided in a memory, each of which contains a search field and a classification key field. Source or destination addresses are stored in the respective search fields along with other information associated with the frame and a compact classification key is stored in the corresponding classification key field. Searches are performed of the respective search fields within the respective lookup tables to determine whether a match exists between the each of the destination and source addresses and other information and the search field within the lookup tables. In the event the searches yield a match, a classification key associated with each respective address is retrieved. Classification keys corresponding to addresses thus retrieved are concatenated and the concatenated value is employed as the basis for a further search of the search field of another one of the lookup tables to identify a classification key which is employed to specify the manner of further processing of the received frame.

    摘要翻译: 公开了一种用于识别,分类和处理在计算机网络中的帧处理器处接收的帧的改进的方法和装置。 在帧处理器的输入端口接收到帧之后,从帧解析源和目的地址。 在存储器中提供多个查找表,每个查找表包含搜索字段和分类关键字段。 源或目的地地址与其他与该帧相关的信息存储在相应的搜索字段中,并且紧凑的分类密钥存储在相应的分类密钥字段中。 对相应查找表内的各搜索字段执行搜索,以确定目的地和源地址中的每一个与查找表中的其他信息和搜索字段之间是否存在匹配。 在搜索产生匹配的情况下,检索与每个相应地址相关联的分类密钥。 对应于如此检索的地址的分类密钥被连接,并且将级联值用作进一步搜索另一个查找表的搜索字段的基础,以识别用于指定进一步处理的方式的分类密钥 收到帧。

    Blended Wing Body Unmanned Aerial Vehicle
    4.
    发明申请
    Blended Wing Body Unmanned Aerial Vehicle 审中-公开
    混合翼身无人机

    公开(公告)号:US20100123047A1

    公开(公告)日:2010-05-20

    申请号:US12271556

    申请日:2008-11-14

    IPC分类号: B64C3/10 B64C3/14

    摘要: A Blended Wing Body SUAV and MUAV is disclosed having a novel airfoil profile, wing configuration, rigging and tractor pull propeller placement that provide improved stability and safety characteristics over prior art SUAVs and MUAVs of comparable size and weight. This unique blended wing design includes wing twist on the outboard wing and an inverted “W” shaped planform to provide lateral and longitudinal stability, and smooth, even flight characteristics throughout the range of the expected flight envelope. These flight characteristics are crucial to providing a stable reconnaissance platform with favorable stall speeds, an increased payload and the ability to hand launch without the danger of exposing ones hands or wrist to a propeller.

    摘要翻译: 混合翼体SUAV和MUAV被公开具有新颖的机翼轮廓,机翼构造,索具和拖拉机拉拔螺旋桨放置,其提供相当于相当尺寸和重量的现有技术的SUAV和MUAV的改进的稳定性和安全性。 这种独特的混合翼设计包括在外侧机翼上的机翼扭转和倒置的“W”形平台,以提供横向和纵向的稳定性,以及在预期飞行包线的整个范围内的平滑,均匀的飞行特性。 这些飞行特性对于提供稳定的侦察平台,具有良好的失速速度,增加的有效载荷和手动发射的能力,而不会将一只手或手腕暴露于螺旋桨的危险至关重要。

    Controller with automatic generation of linked list of data transfer descriptors for sequential commands, with linked list being used for execution of sequential data transfers
    5.
    发明授权
    Controller with automatic generation of linked list of data transfer descriptors for sequential commands, with linked list being used for execution of sequential data transfers 有权
    控制器,用于自动生成用于顺序命令的数据传输描述符的链表,链表用于执行顺序数据传输

    公开(公告)号:US06205494B1

    公开(公告)日:2001-03-20

    申请号:US09215414

    申请日:1998-12-18

    IPC分类号: G06F1324

    CPC分类号: G06F13/38

    摘要: A command queuing engine in a target controller ASIC automatically detects sequential commands received from an initiator and generates a linked list of data transfer descriptors for the sequential commands. The data transfer descriptors are automatically processed by the command queuing engine to reduce command overhead from interrupt processing by a microprocessor in the target controller, thereby improving the performance of the target controller.

    摘要翻译: 目标控制器ASIC中的命令排队引擎自动检测从启动器接收的顺序命令,并生成用于顺序命令的数据传输描述符的链表。 数据传输描述符由命令排队引擎自动处理,以减少由目标控制器中的微处理器进行的中断处理的命令开销,从而提高目标控制器的性能。

    Processing Host Transfer Requests for Direct Block Access Storage Devices
    6.
    发明申请
    Processing Host Transfer Requests for Direct Block Access Storage Devices 有权
    处理直接访问存储设备的主机传输请求

    公开(公告)号:US20110072173A1

    公开(公告)日:2011-03-24

    申请号:US12873450

    申请日:2010-09-01

    IPC分类号: G06F5/00 G06F12/10

    摘要: Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.

    摘要翻译: 所描述的实施例提供了主机子系统,其生成与所接收的主机数据传送请求相对应的主机上下文。 可编程序定序器基于主机上下文生成一个或多个定序器上下文。 每个定序器上下文对应于主机数据传输请求的至少一部分。 定序器上下文被提供给媒体控制器的缓冲子系统。 对于主机读取请求,缓冲器子系统从对应的缓冲器或存储介质检索与读取请求的定序器上下文相关联的数据,并将与定序器上下文相关联的数据发送到主机设备。 对于主机写入请求,缓冲器子系统从主机设备接收与主机上下文相关联的数据,并将与写入请求的定序器上下文相关联的数据存储到相应的缓冲器或存储介质。

    Method for memory allocation in a disk drive employing a chunk array and
identifying a first available element for write caching
    8.
    发明授权
    Method for memory allocation in a disk drive employing a chunk array and identifying a first available element for write caching 失效
    一种采用块阵列并识别用于写入高速缓存的第一可用元素的磁盘驱动器中的内存分配方法

    公开(公告)号:US6092150A

    公开(公告)日:2000-07-18

    申请号:US398566

    申请日:1999-09-16

    IPC分类号: G06F3/06 G06F12/02 G06F12/08

    摘要: The disk drive provides a method of adaptively managing a cache segment divided into chunks by defining an unavailable data type to be stored in an element of a chunk array which indicates that the chunk is not available, and defining an available data type to be stored in an element of the chunk array that indicates the chunk is available and that indicates the number of consecutive chunks that are available. The disk drive also computes a number of chunks needed to fit the request length and scans the chunk array to find a first available element whose available data type meets a predetermined criteria for the number of chunks needed to fit the request length.

    摘要翻译: 磁盘驱动器提供了一种通过定义要存储在块阵列的元素中的不可用数据类型来自适应地管理被划分成块的高速缓存段的方法,其指示块不可用,并且定义可存储的数据类型 指示块的块组件的元素可用,并指示可用的连续块的数量。 磁盘驱动器还计算适合请求长度所需的大量块,并扫描块阵列以找到其可用数据类型满足适合请求长度所需的块数的预定标准的第一可用元素。

    Disk drive cache system using a dynamic priority sequential stream of
data segments continuously adapted according to prefetched sequential
random, and repeating types of accesses
    9.
    发明授权
    Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses 失效
    磁盘驱动器缓存系统使用根据预取的顺序随机连续调整的数据段的动态优先顺序流,并重复访问类型

    公开(公告)号:US6092149A

    公开(公告)日:2000-07-18

    申请号:US864525

    申请日:1997-05-28

    摘要: A magnetic disk drive with a caching system includes an intelligent interface to communicate with a host, a magnetic disk and a cache memory to buffer data transferred to and from the host. The caching system maximizes drive performance based on past access history. The caching system alters execution of commands by coalescing commands or executing internal commands in parallel. The caching system anticipates data requests by using a prefetch to store data that may be requested. The caching system divides the cache memory into segments to store multiple streams of data. The number of segments may be continuously adapted according to the types of access to maximize performance by maintaining a segment for each sequential stream of data. The caching system uses a dynamic priority list to determine segments to maintain and discard. Each segment is monitored to determine access types such as sequential, random, and repeating. The access type determines the amount of data to prefetch and to save, including a minimum and maximum prefetch. The caching system may prescan the cache memory during prefetch to alter the prefetch amount in response to a command request. The caching system may wait for a cache memory access that has not yet occurred. An initiator changes the caching parameters though a mode page.

    摘要翻译: 具有缓存系统的磁盘驱动器包括用于与主机通信的智能接口,磁盘和高速缓冲存储器,以缓冲传送到主机的数据。 缓存系统根据过去的访问历史来最大化驱动器性能。 缓存系统通过并行命令或并行执行内部命令来改变执行命令。 缓存系统通过使用预取来存储可能请求的数据来预期数据请求。 缓存系统将高速缓存存储器分割成段以存储多个数据流。 可以根据访问的类型连续地调整段的数量,以通过维护每个顺序的数据流的段来最大化性能。 缓存系统使用动态优先级列表来确定要维护和丢弃的段。 监视每个段以确定访问类型,如顺序,随机和重复。 访问类型确定要预取和保存的数据量,包括最小和最大预取。 缓存系统可以在预取期间预扫描高速缓冲存储器以响应于命令请求改变预取量。 缓存系统可能会等待尚未发生的高速缓存存储器访问。 发起者通过模式页面来更改缓存参数。

    Method and apparatus for fault-tolerant computer system having
expandable processor section
    10.
    发明授权
    Method and apparatus for fault-tolerant computer system having expandable processor section 失效
    具有可扩展处理器部分的容错计算机系统的方法和装置

    公开(公告)号:US4816990A

    公开(公告)日:1989-03-28

    申请号:US927746

    申请日:1986-11-05

    摘要: A computer system of the type having a processor section, a memory section, an input-output section, a system clock, and a system bus for communicating signals between the sections, accommodates a variable number of processor units in the processor section. The processor section hence is expandable. Synchronization is distributed in that each processor unit can synchronize all the units in the processor section. The processor units arbitrate for access to the system bus, and respond to interrupts, on a distributed basis. A distribution counter in each processor unit provides a periodically sequencing unique count to distribute tasks among the processor units.

    摘要翻译: 具有处理器部分,存储器部分,输入输出部分,系统时钟和用于在部分之间传送信号的系统总线的类型的计算机系统在处理器部分中容纳可变数量的处理器单元。 因此,处理器部分是可扩展的。 分布在同步中,每个处理器单元可以同步处理器部分中的所有单元。 处理器单元仲裁访问系统总线,并在分布式基础上响应中断。 每个处理器单元中的分配计数器提供周期性排序唯一计数以在处理器单元之间分配任务。