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公开(公告)号：US08426745B2
公开(公告)日：2013-04-23
申请号：US12868659
申请日：2010-08-25
CPC分类号： H01L28/60 , H01L23/5228 , H01L28/24 , H01L2924/0002 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.
摘要翻译： 一种用于半导体器件的方法和结构，其提供诸如电阻器等薄膜电阻（TFR）层等不影响较薄层的金属层（例如互连层）的蚀刻。 在一个实施例中，在金属层的蚀刻期间，TFR电阻层由图案化的保护层保护，并为金属层提供底层。 在另一个实施例中，在提供图案化的金属层之后形成TFR层。 金属层可以提供例如电路电阻器的端盖。
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公开(公告)号：US20110128692A1
公开(公告)日：2011-06-02
申请号：US12868659
申请日：2010-08-25
CPC分类号： H01L28/60 , H01L23/5228 , H01L28/24 , H01L2924/0002 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.
摘要翻译： 一种用于半导体器件的方法和结构，其提供诸如电阻器等薄膜电阻（TFR）层等不影响较薄层的金属层（例如互连层）的蚀刻。 在一个实施例中，在金属层的蚀刻期间，TFR电阻层由图案化的保护层保护，并为金属层提供底层。 在另一个实施例中，在提供图案化的金属层之后形成TFR层。 金属层可以提供例如电路电阻器的端盖。
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3.发明授权Method of manufacturing a junction barrier Schottky diode with dual silicides 有权制造具有双重硅化物的结屏障肖特基二极管的方法公开(公告)号：US08101511B2
公开(公告)日：2012-01-24
申请号：US12774762
申请日：2010-05-06
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。
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公开(公告)号：US20110156810A1
公开(公告)日：2011-06-30
申请号：US12944836
申请日：2010-11-12
IPC分类号： G11C7/16 , H01L29/78 , H01L21/336
CPC分类号： H01L29/782 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/7806 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： Embodiments relate generally to voltage converter structures including a diffused metal oxide semiconductor (DMOS) field effect transistors (FET). Embodiments include the combination of DMOS devices (e.g., FETs with isolated bodies from the substrate) with Schottky diodes on a single semiconductor die. The Schottky diode can be integrated into a cell of a DMOS device by forming an N-type area in the P-body region of the DMOS device.
摘要翻译： 实施例一般涉及包括扩散金属氧化物半导体（DMOS）场效应晶体管（FET）的电压转换器结构。 实施例包括DMOS器件（例如，具有来自衬底的隔离体的FET）与单个半导体管芯上的肖特基二极管的组合。 通过在DMOS器件的P体区域中形成N型区域，可以将肖特基二极管集成到DMOS器件的单元中。
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公开(公告)号：US07700977B2
公开(公告)日：2010-04-20
申请号：US12037569
申请日：2008-02-26
申请人： Michael David Church , Alexander Kalnitsky , Lawrence George Pearce , Michael Ray Jayne , Thomas Andrew Jochum
发明人： Michael David Church , Alexander Kalnitsky , Lawrence George Pearce , Michael Ray Jayne , Thomas Andrew Jochum
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L27/0255 , H01L27/0814
摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.
摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。
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6.发明申请公开(公告)号：US20120122308A1
公开(公告)日：2012-05-17
申请号：US13356624
申请日：2012-01-23
IPC分类号： H01L21/8222
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。
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公开(公告)号：US07750426B2
公开(公告)日：2010-07-06
申请号：US11849565
申请日：2007-09-04
IPC分类号： H01L27/095 , H01L29/47 , H01L31/07
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。
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8.发明授权Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions 失效制造具有加强热电子发生区域的增强型EPROM结构的方法公开(公告)号：US06492225B1
公开(公告)日：2002-12-10
申请号：US10026346
申请日：2001-12-20
申请人： Michael David Church
发明人： Michael David Church
IPC分类号： H01L218242
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7883
摘要： An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
摘要翻译： EPROM结构包括与电容器集成的NMOS晶体管。 NMOS晶体管的端子名称遵循常规命名法：漏极，源极，主体和栅极。 NMOS晶体管的栅极直接连接到电容器板之一。 在这种配置中，现在将栅极称为“浮动栅极”。 电容器的剩余侧称为“控制栅极”。
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9.发明授权Method of manufacturing junction barrier schottky diode with dual silicides 有权制造具有双重硅化物的结型肖特基二极管的方法公开(公告)号：US08647971B2
公开(公告)日：2014-02-11
申请号：US13356624
申请日：2012-01-23
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。
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公开(公告)号：US20100314708A1
公开(公告)日：2010-12-16
申请号：US12868346
申请日：2010-08-25
IPC分类号： H01L29/872
CPC分类号： H01L29/66143 , H01L27/0629 , H01L29/063 , H01L29/0692 , H01L29/872
摘要： A junction barrier Schottky diode has an N-type well having a surface and a first peak impurity concentration; a P-type anode region in the surface of the well, and having a second peak impurity concentration; an N-type cathode contact region in the surface of the well and laterally spaced from a first wall of the anode region, and having a third peak impurity concentration; and a first N-type region in the surface of the well and laterally spaced from a second wall of the anode region, and having a fourth impurity concentration. The center of the spaced region between the first N-type region and the second wall of the anode region has a fifth peak impurity concentration. An ohmic contact is made to the anode region and cathode contact region, and a Schottky contact is made to the first N-type region. The first and fifth peak impurity concentrations are less than the fourth peak impurity concentration, and the fourth peak impurity concentration is less that the second and third peak impurity concentrations.
摘要翻译： 接合势垒肖特基二极管具有具有表面和第一峰值杂质浓度的N型阱; 阱的表面中的P型阳极区，具有第二峰杂质浓度; 在所述阱的表面中的N型阴极接触区域，并且与所述阳极区域的第一壁横向间隔开，并且具有第三峰值杂质浓度; 以及在所述阱的表面中的第一N型区域，并且与所述阳极区域的第二壁横向间隔开，并且具有第四杂质浓度。 阳极区域的第一N型区域和第二壁之间的间隔区域的中心具有第五峰值杂质浓度。 对阳极区域和阴极接触区域进行欧姆接触，并且对第一N型区域进行肖特基接触。 第一和第五峰杂质浓度小于第四峰杂质浓度，第四峰杂质浓度小于第二和第三峰杂质浓度。
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