-
1.发明授权Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same 有权连接到磁性隧道结并与金属导体自对准的二极管及其形成方法公开(公告)号：US06562634B2
公开(公告)日：2003-05-13
申请号：US09811759
申请日：2001-03-20
IPC分类号： H01L2100
CPC分类号： H01L27/224 , B82Y10/00
摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.
摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹陷的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共用非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。
-
2.发明授权Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same 失效具有超锐P-N结的半导体装置及其制造方法公开(公告)号：US06180444B2
公开(公告)日：2001-01-30
申请号：US09025710
申请日：1998-02-18
IPC分类号： H01L218234
CPC分类号： H01L29/66136 , H01L27/0814 , H01L29/861 , H01L29/868
摘要： A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.
摘要翻译： 诸如PN或PIN结二极管的半导体器件包括具有第一导电类型并且安装在金属地址线上的第一半导体层，以及具有第二导电类型并安装在第一半导体上的第二半导体层 材料。 二极管优选具有基本上不超过约1微米的厚度，并且二极管包括限定在小于约0.1微米厚度的P-N结。 在优选实施例中，该方法包括沉积具有第一导电类型的第一半导体层，沉积第二本征层，退火以将两层转换成多晶层，将第二导电类型的离子注入到第二层中，以及退火以转换 第二层为多晶。 结果是具有超锋利p-n结的二极管。
-
3.发明授权Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same 有权具有超锐P-N结的半导体装置及其制造方法公开(公告)号：US06351023B1
公开(公告)日：2002-02-26
申请号：US09689660
申请日：2000-10-13
IPC分类号： H01L2906
CPC分类号： H01L29/66136 , H01L27/0814 , H01L29/861 , H01L29/868
摘要： A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.
摘要翻译： 诸如PN或PIN结二极管的半导体器件包括具有第一导电类型并且安装在金属地址线上的第一半导体层，以及具有第二导电类型并安装在第一半导体上的第二半导体层 材料。 二极管优选具有基本上不超过约1微米的厚度，并且二极管包括限定在小于约0.1微米厚度的P-N结。 在优选实施例中，该方法包括沉积具有第一导电类型的第一半导体层，沉积第二本征层，退火以将两层转换成多晶层，将第二导电类型的离子注入到第二层中，以及退火以转换 第二层为多晶。 结果是具有超锋利p-n结的二极管。
-
4.发明授权Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same 有权连接到磁性隧道结并与金属导体自对准的二极管及其形成方法公开(公告)号：US06242770B1
公开(公告)日：2001-06-05
申请号：US09144067
申请日：1998-08-31
IPC分类号： H01L2976
CPC分类号： H01L27/224 , B82Y10/00
摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor form above a magnetic tunnel junction formed on the diode. The diode and first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.
摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹入的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共享非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。
-
5.发明授权公开(公告)号：US06269040B1
公开(公告)日：2001-07-31
申请号：US09603632
申请日：2000-06-26
IPC分类号： G11C702
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1051 , G11C7/18
摘要： An interconnection network for connecting memory cells to sense amplifiers in a memory device includes a plurality of sub-arrays having memory cells, a plurality of switch units each of which is associated with a corresponding one of the plurality of sub-arrays, and true and complement input lines of the sense amplifiers each of which receives data from a selected memory cell via an input line and reference from reference cells via the other input line. The reference, which is a mid-level of data in the memory cells, is obtained from a reference cell having the mid-level value. Alternatively, a mid-level reference may be obtained by averaging data of logic values “1” and “0” stored in different reference cells. The reference cells may be disposed in the sub-arrays or outside the sub-arrays. The interconnection network of the present invention has symmetric configuration so that networks of the input lines of the sense amplifiers have substantially equal structure. Both inputs of a sense amplifier have substantially equal number of connections to data columns and reference columns.
摘要翻译： 用于将存储器单元连接到存储器件中的感测放大器的互连网络包括具有存储器单元的多个子阵列，多个开关单元，每个开关单元与多个子阵列中的相应一个子阵列相关联， 读出放大器的补码输入线，每个读出放大器经由输入线从参考单元经由输入线接收数据，并经由另一输入线从参考单元接收数据。 作为存储器单元中的数据中间值的参考是从具有中间值的参考单元获得的。 或者，可以通过平均存储在不同参考单元中的逻辑值“1”和“0”的数据来获得中间级参考。 参考单元可以设置在子阵列中或子阵列外部。 本发明的互连网络具有对称配置，使得感测放大器的输入线的网络具有基本相同的结构。 读出放大器的两个输入端具有与数据列和参考列基本上相等数量的连接。
-
6.发明授权Magnetic random access memory using a non-linear memory element select mechanism 有权磁性随机存取存储器采用非线性存储元件选择机制公开(公告)号：US06515897B1
公开(公告)日：2003-02-04
申请号：US09549211
申请日：2000-04-13
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A non-volatile memory array having a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping first plurality of traces at a plurality of intersection regions, and a plurality of memory cells. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one memory cell includes a non-linear magnetic tunnel junction storage element. The non-linear magnetic tunnel junction storage element has at least a first ferromagnetic layer, a barrier layer and a second ferromagnetic layer. The non-linear magnetic tunnel junction storage element has a non-linearity that is defined by a current having a first magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 0.5 VA that is ten times or more smaller than a current having a second magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 1 VA, where VA is an operating voltage for a memory cell. The non-linearity is used for minimizing sneak currents through unselected cells, and allowing read or write selection of a particular memory element in a large array.
摘要翻译： 一种非易失性存储器阵列，其具有衬底，形成在衬底上的第一多个导电迹线，形成在衬底上的第二多个导电迹线，并且在多个交叉区域上与第一多个迹线重叠， 记忆细胞 每个存储器单元位于第一多个迹线之一和第二多个迹线中的一个之间的交叉区域。 至少一个存储单元包括非线性磁性隧道结存储元件。 非线性磁性隧道结存储元件具有至少第一铁磁层，阻挡层和第二铁磁层。 非线性磁性隧道结存储元件具有非线性，其由具有流过非线性磁性隧道结存储元件的第一幅度的电流限定，用于横跨非线性磁性隧道结存储元件的偏置约为 0.5VA是比具有第二幅度的电流的十倍或更小，该电流流过非线性磁性隧道结存储元件，用于跨过非线性磁性隧道结存储元件的约1VA的偏压，其中VA是操作的 一个存储单元的电压。 非线性用于通过未选择的单元最小化潜行电流，并允许以大阵列对特定存储器元件进行读取或写入选择。
-
7.发明授权Magnetic random access memory using a series tunnel element select mechanism 有权磁性随机存取存储器采用串联隧道元素选择机制公开(公告)号：US06331944B1
公开(公告)日：2001-12-18
申请号：US09549172
申请日：2000-04-13
IPC分类号： G11C1300
CPC分类号： H01L27/224 , G11C11/15
摘要： A non-volatile memory array includes first and second pluralities of electrically conductive traces formed on a substrate. The second plurality of electrically conductive traces overlap first plurality of traces at a plurality of intersection regions. Each of a plurality of memory cells is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one of the memory cells includes a non-linear selection element in series with a magnetic tunnel junction storage element. The non-linear selection element includes at least a first metallic electrode layer, a barrier layer and a second metallic electrode layer metal. The non-linear selection element has a non-linearity defined by a current having a first magnitude flowing through the non-linear selection element for a first bias voltage across the non-linear selection element that is ten times or more smaller than a current having a second magnitude flowing through the non-linear selection element for a second bias voltage across the non-linear selection element, such that the second bias voltage is about two times greater than the first bias voltage. The magnetic tunnel junction storage element includes at least a first ferromagnetic layer, a thin insulating layer and a second ferromagnetic layer.
摘要翻译： 非易失性存储器阵列包括形成在衬底上的第一和第二多个导电迹线。 第二多个导电迹线在多个交叉区域处与第一多个迹线重叠。 多个存储器单元中的每一个位于第一多个迹线中的一个和第二多个迹线中的一个之间的交叉区域。 至少一个存储单元包括与磁性隧道结存储元件串联的非线性选择元件。 非线性选择元件至少包括第一金属电极层，阻挡层和第二金属电极层金属。 非线性选择元件具有由具有流过非线性选择元件的第一幅度的电流定义的非线性，该电流是非线性选择元件的跨越非线性选择元件的第一偏置电压的十倍或更小， 第二幅度流经所述非线性选择元件，以跨越所述非线性选择元件的第二偏置电压流动，使得所述第二偏置电压大约是所述第一偏置电压的两倍。 磁性隧道结存储元件至少包括第一铁磁层，薄绝缘层和第二铁磁层。
-
8.发明授权Data-dependent field compensation for writing magnetic random access memories 失效用于写入磁随机存取存储器的数据相关磁场补偿公开(公告)号：US06404671B1
公开(公告)日：2002-06-11
申请号：US09933584
申请日：2001-08-21
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A field compensation circuit for selectively writing one or more selected magnetic memory cells in a magnetic random access memory (MRAM) includes a controller for detecting a characteristic representative of an anticipated interaction between a magnetic field emanating from a bit line corresponding to a selected memory cell and at least one stray magnetic field emanating from one or more bit lines associated with one or more memory cells in close relative proximity to the selected memory cell. A control signal generated by the controller is indicative of the detected characteristic. The field compensation circuit further includes a programmable current source operatively coupled to the bit line corresponding to the selected memory cell, the programmable current source including an input for receiving the control signal. The programmable current source generates a write current having a magnitude which varies in response to the control signal. In this manner, the write current flowing through a given bit line corresponding to a selected memory cell can be selectively adjusted to compensate for magnetic field interaction with adjacent bit lines.
摘要翻译： 一种用于选择性地将一个或多个所选择的磁存储器单元写入磁随机存取存储器（MRAM）的场补偿电路包括一个控制器，用于检测表示从对应于所选存储单元的位线发出的磁场之间的预期相互作用的特性 以及从与所选择的存储器单元相对靠近的一个或多个存储器单元相关联的一个或多个位线发出的至少一个杂散磁场。 由控制器产生的控制信号表示检测到的特性。 场补偿电路还包括可操作地耦合到对应于所选存储单元的位线的可编程电流源，可编程电流源包括用于接收控制信号的输入端。 可编程电流源产生具有响应于控制信号而变化的幅度的写入电流。 以这种方式，可以选择性地调节流过与所选存储单元相对应的给定位线的写入电流，以补偿与相邻位线的磁场相互作用。
-
公开(公告)号：US6130835A
公开(公告)日：2000-10-10
申请号：US982893
申请日：1997-12-02
IPC分类号： G11C11/15
CPC分类号： G11C11/15
摘要： A nonvolatile memory array includes a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping the first plurality of traces at a plurality of intersection regions, and a plurality of memory cells formed on the substrate. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of trace and includes a bidirectionally conducting nonlinear resistance selection device and a magneto-resistive element electrically coupled in series with the selection device. The array is biased during a read operation by biasing a selected trace of a first plurality of electrically conductive traces at a first bias potential. All other traces of the first plurality of conductive traces are biased at a second bias potential. A selected trace of a second plurality of conductive traces is biased at a third bias potential. Lastly, all other traces of the second plurality of conductive traces are biased at the first bias potential.
摘要翻译： 非易失性存储器阵列包括衬底，形成在衬底上的第一多个导电迹线，形成在衬底上的第二多个导电迹线，并且在多个交叉区域与第一多个迹线重叠，以及多个存储器 在基底上形成的细胞。 每个存储单元位于第一多个迹线之一和第二多个迹线中的一个之间的交叉区域，并且包括双向传导非线性电阻选择装置和与选择装置串联电耦合的磁阻元件。 通过在第一偏置电位偏置第一多个导电迹线的选定轨迹，在读取操作期间该阵列被偏置。 第一多个导电迹线中的所有其它迹线被偏置在第二偏置电位。 第二多个导电迹线的选定迹线被偏置在第三偏置电位。 最后，第二多个导电迹线中的所有其它迹线被偏置在第一偏置电位。
-
公开(公告)号：US5991193A
公开(公告)日：1999-11-23
申请号：US982995
申请日：1997-12-02
CPC分类号： G11C11/15
摘要： A nonvolatile memory array includes a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping the first plurality of traces at a plurality of intersection regions, and a plurality of memory cells formed on the substrate. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces and includes a bidirectionally conducting nonlinear resistance selection device and a magneto-resistive element electrically coupled in series with the selection device. The array is biased during a read operation by biasing a selected trace of a first plurality of electrically conductive traces at a first bias potential. All other traces of the first plurality of conductive traces are biased at a second bias potential. A selected trace of a second plurality of conductive traces is biased at a third bias potential. Lastly, all other traces of the second plurality of conductive traces are biased at the first bias potential.
摘要翻译： 非易失性存储器阵列包括衬底，形成在衬底上的第一多个导电迹线，形成在衬底上的第二多个导电迹线，并且在多个交叉区域与第一多个迹线重叠，以及多个存储器 在基底上形成的细胞。 每个存储器单元位于第一多个迹线中的一个与第二多个迹线中的一个之间的交叉区域，并且包括双向传导非线性电阻选择器件和与选择器件串联电耦合的磁阻元件。 通过在第一偏置电位偏置第一多个导电迹线的选定轨迹，在读取操作期间该阵列被偏置。 第一多个导电迹线中的所有其它迹线被偏置在第二偏置电位。 第二多个导电迹线的选定迹线被偏置在第三偏置电位。 最后，第二多个导电迹线中的所有其它迹线被偏置在第一偏置电位。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.029 秒)
