公开(公告)号：US06562634B2

公开(公告)日：2003-05-13

申请号：US09811759

申请日：2001-03-20

申请人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

发明人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

IPC分类号： H01L2100

CPC分类号： H01L27/224 ,  B82Y10/00

摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹陷的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共用非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。

公开(公告)号：US06242770B1

公开(公告)日：2001-06-05

申请号：US09144067

申请日：1998-08-31

申请人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

发明人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

IPC分类号： H01L2976

CPC分类号： H01L27/224 ,  B82Y10/00

摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor form above a magnetic tunnel junction formed on the diode. The diode and first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹入的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共享非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。

公开(公告)号：US08039888B2

公开(公告)日：2011-10-18

申请号：US11848597

申请日：2007-08-31

申请人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

发明人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

公开(公告)号：US06014310A

公开(公告)日：2000-01-11

申请号：US177143

申请日：1998-10-21

申请人： Gary Bela Bronner ,  Stephan Alan Cohen ,  David Mark Dobuzinsky ,  Jeffrey Peter Gambino ,  Herbert Lei Ho ,  Karen Popek Madden

发明人： Gary Bela Bronner ,  Stephan Alan Cohen ,  David Mark Dobuzinsky ,  Jeffrey Peter Gambino ,  Herbert Lei Ho ,  Karen Popek Madden

IPC分类号： H01L21/318 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/06 ,  B05D5/12

CPC分类号： H01L21/3144 ,  H01L21/31604 ,  H01L21/3185

摘要： A composite dielectric material useful in advanced memory applications such as dynamic random access memory (DRAM) cells is provided. The composite dielectric material of the present invention includes a mixed oxide such as TiO.sub.2 or Ta.sub.2 O.sub.5 that is interdiffused into a Si.sub.3 N.sub.4 film. Capacitors including the composite dielectric material of the present invention are also disclosed.

摘要翻译： 提供了一种用于诸如动态随机存取存储器（DRAM）单元的高级存储器应用中的复合介电材料。 本发明的复合电介质材料包括相互扩散到Si 3 N 4膜中的诸如TiO 2或Ta 2 O 5的混合氧化物。 还公开了包括本发明的复合介电材料的电容器。

公开(公告)号：US06974991B2

公开(公告)日：2005-12-13

申请号：US10696151

申请日：2003-10-29

申请人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bela Bronner ,  Carl John Radens ,  Oleg G. Gluschenkov

发明人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bela Bronner ,  Carl John Radens ,  Oleg G. Gluschenkov

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10864 ,  H01L27/10867

摘要： In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.

公开(公告)号：US06087225A

公开(公告)日：2000-07-11

申请号：US18939

申请日：1998-02-05

申请人： Gary Bela Bronner ,  Badih El-Kareh ,  Stanley Everett Schuster

发明人： Gary Bela Bronner ,  Badih El-Kareh ,  Stanley Everett Schuster

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L21/823842

摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

摘要翻译： 在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚和薄栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，并且逻辑电路可以由同一芯片上的薄氧化物FET构成。 首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。 堆叠包括栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。 选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。 在再曝光的晶片上形成更薄的栅氧化层。 接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。 在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。 最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

公开(公告)号：US09305644B2

公开(公告)日：2016-04-05

申请号：US14125913

申请日：2012-06-22

申请人： Mark D. Kellam ,  Gary Bela Bronner

发明人： Mark D. Kellam ,  Gary Bela Bronner

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： G11C13/004 ,  G11C13/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.

摘要翻译： 电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。 双端子存取装置影响电阻存储单元的电流 - 电压特性。 电阻存储器还包括电路，跨越电阻存储单元施加具有设定极性的设定脉冲，以将电阻存储单元设置为在施加设置脉冲之后保持的低电阻状态，具有复位极性的复位脉冲 与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态 的电阻存储单元，而不改变电阻存储单元的电阻状态。

公开(公告)号：US06638815B1

公开(公告)日：2003-10-28

申请号：US10280971

申请日：2002-10-25

申请人： Gary Bela Bronner ,  Ramachandra Divakaruni

发明人： Gary Bela Bronner ,  Ramachandra Divakaruni

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

摘要： In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulator layer, forming a vertical hardmask on the inner trench walls above the sacrificial insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the vertical transistor.

摘要翻译： 在基于垂直晶体管的半导体结构中，通过以下方式解决了深沟槽电容器的节点与垂直晶体管的下电极之间可靠的电连接的问题; 沉积牺牲绝缘体层，在牺牲绝缘体上方的内沟槽壁上形成垂直硬掩模，然后剥离绝缘体以露出基底壁; 将掺杂剂扩散到衬底壁中以形成埋入带的自对准延伸部; 沉积最后的栅极绝缘体; 然后形成垂直晶体管的上部。

公开(公告)号：US20080272398A1

公开(公告)日：2008-11-06

申请号：US11848597

申请日：2007-08-31

申请人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

发明人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

公开(公告)号：US6084276A

公开(公告)日：2000-07-04

申请号：US337904

申请日：1999-06-22

申请人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

发明人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/76 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/76229 ,  H01L21/76237

摘要： A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

摘要翻译： 半导体MOSFET器件形成在硅衬底上，该衬底包括填充有浅沟槽隔离电介质沟槽填充结构并在衬底表面上方延伸的沟槽。 沟槽填充结构具有突出的侧壁，其中衬底中的通道区域具有与沟槽填充结构相邻的拐角区域。 沟道区域在与沟槽区域的中心掺杂一个浓度的掺杂剂的STI沟槽填充结构之间并相邻，在拐角区域具有较高浓度的掺杂剂。 掺杂剂浓度差在通道区域的中心和拐角区域提供基本相等的电子浓度。