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    Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same
    1.
    发明授权
    Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same 有权
    连接到磁性隧道结并与金属导体自对准的二极管及其形成方法

    公开(公告)号：US06562634B2

    公开(公告)日：2003-05-13

    申请号：US09811759

    申请日：2001-03-20

    申请人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    发明人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    IPC分类号： H01L2100

    CPC分类号： H01L27/224 ,  B82Y10/00

    摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

    摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹陷的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共用非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。

    Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same
    2.
    发明授权
    Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same 有权
    连接到磁性隧道结并与金属导体自对准的二极管及其形成方法

    公开(公告)号：US06242770B1

    公开(公告)日：2001-06-05

    申请号：US09144067

    申请日：1998-08-31

    申请人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    发明人： Gary Bela Bronner ,  Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    IPC分类号： H01L2976

    CPC分类号： H01L27/224 ,  B82Y10/00

    摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor form above a magnetic tunnel junction formed on the diode. The diode and first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

    摘要翻译： 磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹入的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。 二极管和第一薄膜导体共享非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。

    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
    3.
    发明授权
    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same 有权
    具有超锐P-N结的半导体装置及其制造方法

    公开(公告)号：US06351023B1

    公开(公告)日：2002-02-26

    申请号：US09689660

    申请日：2000-10-13

    申请人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    发明人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    IPC分类号： H01L2906

    CPC分类号： H01L29/66136 ,  H01L27/0814 ,  H01L29/861 ,  H01L29/868

    摘要： A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

    摘要翻译： 诸如PN或PIN结二极管的半导体器件包括具有第一导电类型并且安装在金属地址线上的第一半导体层，以及具有第二导电类型并安装在第一半导体上的第二半导体层 材料。 二极管优选具有基本上不超过约1微米的厚度，并且二极管包括限定在小于约0.1微米厚度的P-N结。 在优选实施例中，该方法包括沉积具有第一导电类型的第一半导体层，沉积第二本征层，退火以将两层转换成多晶层，将第二导电类型的离子注入到第二层中，以及退火以转换 第二层为多晶。 结果是具有超锋利p-n结的二极管。

    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
    4.
    发明授权
    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same 失效
    具有超锐P-N结的半导体装置及其制造方法

    公开(公告)号：US06180444B2

    公开(公告)日：2001-01-30

    申请号：US09025710

    申请日：1998-02-18

    申请人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    发明人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    IPC分类号： H01L218234

    CPC分类号： H01L29/66136 ,  H01L27/0814 ,  H01L29/861 ,  H01L29/868

    摘要： A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

    摘要翻译： 诸如PN或PIN结二极管的半导体器件包括具有第一导电类型并且安装在金属地址线上的第一半导体层，以及具有第二导电类型并安装在第一半导体上的第二半导体层 材料。 二极管优选具有基本上不超过约1微米的厚度，并且二极管包括限定在小于约0.1微米厚度的P-N结。 在优选实施例中，该方法包括沉积具有第一导电类型的第一半导体层，沉积第二本征层，退火以将两层转换成多晶层，将第二导电类型的离子注入到第二层中，以及退火以转换 第二层为多晶。 结果是具有超锋利p-n结的二极管。

    Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality
    5.
    发明授权
    Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality 有权
    超低＆kgr 使用含有SiCOH基质官能团和有机致孔剂功能的单一双功能前体的等离子体增强化学气相沉积方法

    公开(公告)号：US08097932B2

    公开(公告)日：2012-01-17

    申请号：US12371180

    申请日：2009-02-13

    申请人： Son Van Nguyen ,  Stephen McConnell Gates ,  Deborah A. Neumayer ,  Alfred Grill

    发明人： Son Van Nguyen ,  Stephen McConnell Gates ,  Deborah A. Neumayer ,  Alfred Grill

    IPC分类号： H01L23/58

    CPC分类号： C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/31695 ,  Y10T428/249921

    摘要： A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.

    摘要翻译： 提供了由具有内置有机致孔剂的单一有机硅前体制备包含Si，C，O和H原子的SiCOH电介质材料的方法。 具有内置有机致孔剂的单一有机硅前体选自具有分子式SiRR1R2R3的硅烷（SiH4）衍生物，具有分子式为R4R5R6-Si-O-Si-R7R8R9的二硅氧烷衍生物和分子式为R10R11R12- Si-O-Si-R13R14-O-Si-R15R16R17其中R和R1-17可以相同也可以不相同，并且可以选自H，烷基，烷氧基，环氧基，苯基，乙烯基，烯丙基，烯基或炔基， 直链，支链，环状，多环，并且可以被含氧，含氮或氟的取代基官能化。 除了该方法之外，本申请还提供了由本发明方法制备的SiCOH电介质以及含有该SiCOH的电子结构。

    Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
    6.
    发明授权
    Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
    多层硬掩模方案，用于SiCOH电介质的无损双重镶嵌加工

    公开(公告)号：US07811926B2

    公开(公告)日：2010-10-12

    申请号：US12198602

    申请日：2008-08-26

    申请人： Nicholas C. M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

    发明人： Nicholas C. M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

    IPC分类号： H01L21/00

    CPC分类号： H01L21/0331 ,  H01L21/76811 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/31667 ,  H01L2924/00

    摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

    摘要翻译： 具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。 本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。 后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

    Interconnect structure with precise conductor resistance and method to form same
    9.
    发明授权
    Interconnect structure with precise conductor resistance and method to form same 有权
    具有精确导体电阻的互连结构和形成相同的方法

    公开(公告)号：US06710450B2

    公开(公告)日：2004-03-23

    申请号：US09795430

    申请日：2001-02-28

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L23532

    CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/76811 ,  H01L21/7684

    摘要： An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics. Covalent bonding is achieved by employing an organosilane having functional groups that are capable of bonding with the top and bottom dielectric layers.

    摘要翻译： 提供了包括旋涂电介质的图案化多层的互连结构及其制造方法。 互连结构包括形成在衬底的表面上的旋涂电介质的图案化多层。 旋涂电介质的图案化多层由底部低k电介质，掩埋蚀刻停止层和顶部低k电介质组成，其中底部和顶部低k电介质具有第一组成，所述掩埋蚀刻 停止层具有与第一组成不同的第二组成，并且掩埋蚀刻停止层共价键合到所述顶部和底部低k电介质。 互连结构还包括形成在旋涂电介质的图案化多层上的抛光停止层; 以及形成在旋涂电介质的图案化多层中的金属导电区域。 通过使用具有能够与顶部和底部电介质层结合的官能团的有机硅烷来实现共价键合。