公开(公告)号：US08288636B1

公开(公告)日：2012-10-16

申请号：US13169197

申请日：2011-06-27

申请人： Stephen Rahn

发明人： Stephen Rahn

IPC分类号： G10D3/10

CPC分类号： G10D1/085 ,  G10H1/32 ,  G10H3/18

摘要： The invention is for a solid body type guitar having a pickup selector switch located closely adjacent to the volume controls. The invention is a specially developed pickup selector switch tip knob having an extension arm which is contoured to conveniently fit the human finger for easy manipulation of the pickup selector switch. The contoured extension arm can have one or both sides contoured to accommodate easy pickup selection from either direction with the guitar player's hand. The invention can be mounted on the pickup selector switch post such that the extension arm is facing either toward the guitar strings or away from the guitar strings.

摘要翻译： 本发明是一种固体式吉他，其具有靠近音量控制器的拾音器选择开关。 本发明是一种特别开发的拾音器选择开关尖端旋钮，其具有延伸臂，该延伸臂的轮廓方便地方便地装配人的手指，以便于拾取选择器开关的操纵。 轮廓延伸臂可以具有一个或两个侧面轮廓，以容纳从吉他手的任一方向拾取选择。 本发明可以安装在拾取选择器开关柱上，使得延伸臂面向吉他琴弦或远离吉他琴弦。

公开(公告)号：US06437401B1

公开(公告)日：2002-08-20

申请号：US09824957

申请日：2001-04-03

申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

IPC分类号： H01L2976

CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

公开(公告)号：US07063921B2

公开(公告)日：2006-06-20

申请号：US10667552

申请日：2003-09-22

申请人： Wolfgang Dettman ,  Josef Mathuni ,  Oliver Fagerer ,  Bettina Schiessl ,  Stephen Rahn

发明人： Wolfgang Dettman ,  Josef Mathuni ,  Oliver Fagerer ,  Bettina Schiessl ,  Stephen Rahn

IPC分类号： G01F9/00 ,  G03C5/00

CPC分类号： G03F1/34 ,  G03F1/30 ,  G03F1/36 ,  G03F1/40 ,  Y10T403/5773

摘要： The invention relates to a method for the production of masks, in particular for the production of alternating phase shift masks (1), or of chromeless phase shift masks or phase shift masks structured by quartz etching, respectively, as well as to a mask (1), in particular photomask, for the production of semiconductor devices, comprising at least one product field area (6a) and a compensation structure (5) positioned outside the product field area (6a), wherein the compensation structure (5) comprises at least one electroconductive region (8b) that is electrically connected with the product field area (6a).

摘要翻译： 本发明涉及一种用于制造掩模的方法，特别是用于生产交替相移掩模（1）或由石英蚀刻构成的无铬相移掩模或相移掩模以及掩模（ 1），特别是光掩模，用于生产半导体器件，包括至少一个产品场区（6a）和位于产品场区（6a）外部的补偿结构（5），其中补偿结构（5） 包括与产品场区域（6a）电连接的至少一个导电区域（8b）。

公开(公告)号：US06613642B2

公开(公告)日：2003-09-02

申请号：US10016075

申请日：2001-12-13

申请人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

公开(公告)号：US06559002B1

公开(公告)日：2003-05-06

申请号：US10032041

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

发明人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L28/84 ,  Y10S438/964

摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.

摘要翻译： 在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和 在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成 微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f） 使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。