公开(公告)号：US06613642B2

公开(公告)日：2003-09-02

申请号：US10016075

申请日：2001-12-13

申请人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

公开(公告)号：US06555430B1

公开(公告)日：2003-04-29

申请号：US09723420

申请日：2000-11-28

申请人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

发明人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/964

摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

摘要翻译： 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

公开(公告)号：US06620724B1

公开(公告)日：2003-09-16

申请号：US10142518

申请日：2002-05-09

申请人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

发明人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

IPC分类号： H01L214763

CPC分类号： H01L28/60 ,  H01L27/10861

摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

摘要翻译： 提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

公开(公告)号：US06399490B1

公开(公告)日：2002-06-04

申请号：US09607131

申请日：2000-06-29

申请人： Rajarao Jammy ,  Cheryl G. Faltermeier ,  Uwe Schroeder ,  Kwong Hon Wong

发明人： Rajarao Jammy ,  Cheryl G. Faltermeier ,  Uwe Schroeder ,  Kwong Hon Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76852 ,  H01L21/7687 ,  H01L27/10861 ,  H01L28/82

摘要： Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350° C. to about 800° C. The ratio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

摘要翻译： 在硅衬底上形成高保形氮化钛的工艺。 四氯化钛和氨的气态反应混合物通过保持在约350℃至约800℃的半导体衬底表面上。四氯化钛与氨的比例为约5：1至20：1。 通过本发明的方法实现的高度的保形性允许TiN层沉积在具有高纵横比的结构上和复杂的三维结构上，而不形成大的接缝或空隙。

公开(公告)号：US08926805B2

公开(公告)日：2015-01-06

申请号：US13561599

申请日：2012-07-30

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D17/02 ,  C25D5/18 ,  C25D5/02 ,  H01L21/288 ,  C25D17/00 ,  H01L21/762

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07667278B2

公开(公告)日：2010-02-23

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括包括包括金属碳化物的栅电极和至少一种制造方法的至少一个FET的互补金属氧化物半导体（CMOS）的半导体器件。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US07598545B2

公开(公告)日：2009-10-06

申请号：US11111592

申请日：2005-04-21

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：US20090179279A1

公开(公告)日：2009-07-16

申请号：US12014511

申请日：2008-01-15

申请人： Veeraraghavan S. Basker ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Lubomyr T. Romankiw

发明人： Veeraraghavan S. Basker ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Lubomyr T. Romankiw

IPC分类号： H01L21/283 ,  H01L29/43 ,  C25D3/00

CPC分类号： C25D3/567 ,  C25D5/02 ,  C25D7/12 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof.

摘要翻译： 公开了用于互补金属氧化物半导体（“CMOS”）应用的稳定金属栅极电极和制造稳定的金属栅电极的方法。 具体地说，金属栅电极通过合金化来稳定化，其中合金包括选自Re，Ru，Pt，Rh，Ni，Al及其组合的金属和选自W，V，Ti ，Ta及其组合。

公开(公告)号：US20090127121A1

公开(公告)日：2009-05-21

申请号：US11940720

申请日：2007-11-15

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D5/00 ,  C25D17/00

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。