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9 条记录 (耗时 0.018 秒)

    Process For Manufacturing Sound Absorbing Cement Tile
    2.
    发明申请
    Process For Manufacturing Sound Absorbing Cement Tile 有权
    制造吸声水泥瓦的工艺

    公开(公告)号：US20060175723A1

    公开(公告)日：2006-08-10

    申请号：US10906142

    申请日：2005-02-04

    申请人： Steven Butler ,  Jorg Bold ,  Eric Millamon ,  Michel Rigaudon

    发明人： Steven Butler ,  Jorg Bold ,  Eric Millamon ,  Michel Rigaudon

    IPC分类号： B29C44/34

    CPC分类号： C04B28/145 ,  B01F5/0473 ,  B01F7/00633 ,  B01F7/22 ,  B28C5/06 ,  B28C5/383 ,  B28C5/40 ,  C04B38/10 ,  C04B2111/0062 ,  C04B2111/52 ,  C04B20/0048 ,  C04B38/0074

    摘要： A continuous process for manufacturing a sound absorbing tile made from a slurry including, quick setting cement, water, fibers and foaming agent, the process including the steps of (i) mixing cementitious material, water, foaming agent but without incorporation of prefabricated foam with fibers into a slurry; subsequently; (ii) injecting and distributing air into the slurry of step (i) to form a cellular slurry; subsequently; (iii) forming tiles or precursor products of tiles from the cellular slurry; and finally; (iv) allowing the cellular slurry to set into the desired tile or a precursor thereof.

    摘要翻译： 一种用于制造由包括快速凝固水泥，水，纤维和发泡剂的浆料制成的吸音砖的连续方法，所述方法包括以下步骤：（i）将水泥质材料，水，发泡剂混合，但不将预制泡沫与 纤维成浆料; 后来; （ii）将空气注入并分配到步骤（i）的浆料中以形成细胞浆液; 后来; （iii）从细胞浆中形成瓷砖或前体产品; 最后 （iv）允许细胞浆液置于所需的瓷砖或其前体中。

    Segmented write bitline system and method
    4.
    发明授权
    Segmented write bitline system and method 有权
    分段写位线系统和方法

    公开(公告)号：US07889582B1

    公开(公告)日：2011-02-15

    申请号：US12046675

    申请日：2008-03-12

    申请人： Steven Butler

    发明人： Steven Butler

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

    摘要： A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operations on the memory cells while maintaining a stability thereof.

    摘要翻译： 提供了一种存储器件，用于在保持其稳定性的同时对存储器单元执行写入操作。 提供了包括多个存储单元的存储器阵列。 此外，提供分段写入位线，用于在保持其稳定性的同时对存储器单元执行写入操作。

    Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps
    5.
    发明授权
    Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps 失效
    用于CMOS集成电路静电放电保护钳的自参考调制电路

    公开(公告)号：US5617283A

    公开(公告)日：1997-04-01

    申请号：US697124

    申请日：1996-08-20

    申请人： David B. Krakauer ,  Kaizad Mistry ,  Steven Butler ,  Hamid Partovi

    发明人： David B. Krakauer ,  Kaizad Mistry ,  Steven Butler ,  Hamid Partovi

    IPC分类号： H02H3/00 ,  H02H9/04

    CPC分类号： H02H9/046 ,  H02H3/006

    摘要： An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.

    摘要翻译： 提供一种ESD保护装置，其包括用于控制其操作的自参考调制电路。 调制电路包括耦合到电阻器的二极管堆叠，并且还在一个实施例中耦合到由信号焊盘电压供电的逆变器，或者在替代实施例中由信号焊盘电压供电的奇数多个串联连接的逆变器。 逆变器链耦合到ESD钳位。 调制电路不需要参考电源电压工作。 ESD保护电路将与ESD相关的电流与IC相连，并将I / O焊盘电压钳制到可接受的ESD事件期间。

    Article of headwear
    6.
    发明申请
    Article of headwear 审中-公开
    头饰文章

    公开(公告)号：US20090205109A1

    公开(公告)日：2009-08-20

    申请号：US11295195

    申请日：2005-12-06

    申请人： Steven Butler

    发明人： Steven Butler

    IPC分类号： A42B1/00 ,  A41D27/08

    CPC分类号： A42B1/062 ,  A42B1/004

    摘要： The present invention relates to an article of headwear having a material representing a sport ball, including stitching resembling the sport ball, covering all or a portion of the brim or head-covering portion of the headwear.

    摘要翻译： 本发明涉及具有代表运动球的材料的头饰物品，其包括类似于运动球的缝合物，覆盖头饰的边缘或头部覆盖部分的全部或一部分。

    Static random access memory having tunable-self-timed control logic circuits
    7.
    发明授权
    Static random access memory having tunable-self-timed control logic circuits 失效
    具有可调谐自定时控制逻辑电路的静态随机存取存储器

    公开(公告)号：US5546354A

    公开(公告)日：1996-08-13

    申请号：US270190

    申请日：1994-07-01

    申请人： Hamid Partovi ,  Steven Butler ,  Luan Tran

    发明人： Hamid Partovi ,  Steven Butler ,  Luan Tran

    IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C8/18

    摘要： A self-timed logic device which produces internal control and timing signals in response to an external signal is described. The circuit includes means responsive to a pulse signal for providing control and timing signals and means responsive to a change in state of a signal fed to said device for providing said pulse signal. The means for providing said pulse further includes means for selectively changing timing characteristics of said device in response to external tuning signals fed to the device. In a preferred embodiment the logic device is a static random access memory.

    摘要翻译： 描述了响应于外部信号产生内部控制和定时信号的自定时逻辑器件。 该电路包括响应于脉冲信号以提供控制和定时信号的装置，以及响应馈送到所述装置的信号的状态改变以提供所述脉冲信号的装置。 用于提供所述脉冲的装置还包括用于响应于馈送到装置的外部调谐信号选择性地改变所述装置的定时特性的装置。 在优选实施例中，逻辑设备是静态随机存取存储器。

    Sealing system in which there is relative sliding motion between a gate and a port
    8.
    发明授权
    Sealing system in which there is relative sliding motion between a gate and a port 有权
    在门和端口之间存在相对滑动运动的密封系统

    公开(公告)号：US06405484B1

    公开(公告)日：2002-06-18

    申请号：US09424658

    申请日：1999-11-29

    申请人： Steven Butler

    发明人： Steven Butler

    IPC分类号： E05D1528

    CPC分类号： C23C14/564 ,  F16J13/18 ,  F16J13/20

    摘要： A sealing system includes a gate (2) which is pivotably mounted to a crank (3) which is mounted for rotation with shaft (1). A spring (5) is disposed between gate (2) and crank (3). The gate (2) includes an O-ring (6) which compresses and slides during closure.

    摘要翻译： 密封系统包括可枢转地安装到曲轴（3）的门（2），该曲柄（3）安装成与轴（1）一起旋转。 在门（2）和曲柄（3）之间设有弹簧（5）。 闸门（2）包括在关闭期间压缩和滑动的O形环（6）。

    Fast tag compare and bank select in set associative cache
    9.
    发明授权
    Fast tag compare and bank select in set associative cache 失效
    快速标签比较和集合相关缓存中的存储区选择

    公开(公告)号：US5353424A

    公开(公告)日：1994-10-04

    申请号：US794865

    申请日：1991-11-19

    申请人： Hamid Partovi ,  William R. Wheeler ,  Michael Leary ,  Michael A. Case ,  Steven Butler ,  Rajesh Khanna

    发明人： Hamid Partovi ,  William R. Wheeler ,  Michael Leary ,  Michael A. Case ,  Steven Butler ,  Rajesh Khanna

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0895 ,  G06F12/0864

    摘要： A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.

    摘要翻译： 用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作，使得在存储器周期中早期产生高速缓存命中或未命中信号。 高速缓存的数据存储器具有两个（或更多个）存储体，每个存储体具有标签存储，并且当标签转换正在进行时，使用索引（低位地址位）分开存取和并行访问两个存储体。 执行两个逐位标签比较，每个标签存储一个，产生两个多位匹配指示，每个标签存储中每个标签位一位。 这两个匹配指示被应用于两个单独的动态NOR门，并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。 比较操作有四个可能的结果：两家银行错失，左岸点击，右岸点击，两家银行都受到打击。 后面的条件表示可能的模糊性，并且都不应该使用数据项，所以发出了错误信号。 使用流通设计，比较器在很大程度上是自定时的，与时钟边沿不同。 银行选择逻辑中的延迟元素允许银行彼此定时，并且采用电流限制器来均衡缺失信号的定时，而不管匹配线的数量如何切换高（这取决于数据）。 产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出，即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点 ，而后来将打开二十条出路。 尽管本文中示出了双向组关联高速缓存作为示例实施例，但是本发明的特征之一是更高级别的关联性，例如四路和八路同样适应。