Gas driven rotation apparatus and method for forming crystalline layers
    2.
    发明申请
    Gas driven rotation apparatus and method for forming crystalline layers 有权
    气体驱动旋转装置及形成结晶层的方法

    公开(公告)号:US20070062455A1

    公开(公告)日:2007-03-22

    申请号:US11224458

    申请日:2005-09-12

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: C23C16/00 C23F1/00

    摘要: A gas driven apparatus and method that can be useful for growing crystalline materials are provided. The gas driven rotation apparatus can include one or more rotatable substrate support members, each of which can be configured to support at least one substrate having a growth surface oriented in a downwardly facing position. The gas driven rotation apparatus can further include one or more drive gas channels adapted to direct the flow of a drive gas to rotate the substrate support member. One or more substrates can be positioned in the apparatus so that the growth surface of each substrate is downwardly oriented. A drive gas can flow through the drive gas channel to rotate the substrate. During rotation, reactant gases can be introduced to contact the downwardly facing growth surface, and epitaxial layers of a crystalline material can thereby be grown in a downward direction.

    摘要翻译: 提供了可用于生长结晶材料的气体驱动装置和方法。 气体驱动的旋转装置可以包括一个或多个可旋转的基板支撑构件,每个可旋转的基板支撑构件可构造成支撑至少一个基板,该基板具有朝向下的位置定向的生长面。 气体驱动旋转装置还可以包括一个或多个驱动气体通道,其适于引导驱动气体的流动以旋转衬底支撑构件。 可以将一个或多个基底定位在装置中,使得每个基底的生长表面向下定向。 驱动气体可以流过驱动气体通道以旋转基板。 在旋转期间,可以引入反应气体以接触朝下的生长表面,从而可以沿向下的方向生长结晶材料的外延层。

    Binary group III-nitride based high electron mobility transistors and methods of fabricating same
    3.
    发明申请
    Binary group III-nitride based high electron mobility transistors and methods of fabricating same 有权
    二元组III族氮化物基高电子迁移率晶体管及其制造方法

    公开(公告)号:US20060244011A1

    公开(公告)日:2006-11-02

    申请号:US11118675

    申请日:2005-04-29

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: H01L29/24

    CPC分类号: H01L29/7783 H01L29/2003

    摘要: Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AlN barrier layer.

    摘要翻译: 提供二元III族氮化物高电子迁移率晶体管(HEMT)和制造二元III族氮化物HEMT的方法。 在一些实施例中,二元III族氮化物HEMT包括第一二元III族氮化物阻挡层,第一阻挡层上的二元III族氮化物沟道层; 以及沟道层上的第二二元组III族氮化物势垒层。 在一些实施例中,二元III族氮化物HEMT包括第一AIN势垒层,GaN沟道层和第二AlN势垒层。

    Co-doping for fermi level control in semi-insulating group III nitrides
    5.
    发明申请
    Co-doping for fermi level control in semi-insulating group III nitrides 有权
    半绝缘III族氮化物中的费米能级控制的共掺杂

    公开(公告)号:US20070015299A1

    公开(公告)日:2007-01-18

    申请号:US11522773

    申请日:2006-09-18

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: H01L21/00

    摘要: Semi-insulating Group III nitride layers and methods of fabricating semi-insulating Group III nitride layers include doping a Group III nitride layer with a shallow level p-type dopant and doping the Group III nitride layer with a deep level dopant, such as a deep level transition metal dopant. Such layers and/or method may also include doping a Group III nitride layer with a shallow level dopant having a concentration of less than about 1×1017 cm−3 and doping the Group III nitride layer with a deep level transition metal dopant. The concentration of the deep level transition metal dopant is greater than a concentration of the shallow level p-type dopant.

    摘要翻译: 半绝缘III族氮化物层和制造半绝缘III族氮化物层的方法包括用浅层p型掺杂剂掺杂III族氮化物层,并用深层掺杂剂掺杂III族氮化物层,例如深度 水平过渡金属掺杂剂。 这样的层和/或方法还可以包括用具有小于约1×10 -3 cm -3的浓度的浅级掺杂剂掺杂III族氮化物层,并掺杂该组 III型氮化物层具有深层过渡金属掺杂剂。 深层过渡金属掺杂剂的浓度大于浅层p型掺杂剂的浓度。

    Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
    6.
    发明申请
    Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same 有权
    碳化硅衬底上的低位错密度III族氮化物层及其制造方法

    公开(公告)号:US20070004184A1

    公开(公告)日:2007-01-04

    申请号:US11169471

    申请日:2005-06-29

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: H01L33/00 H01L21/20

    摘要: Group III nitride semiconductor device structures are provided that include a silicon carbide (SiC) substrate and a Group III nitride epitaxial layer above the SiC substrate. The Group III nitride epitaxial layer has a dislocation density of less than about 4×108 cm−2 and/or an isolation voltage of at least about 50V.

    摘要翻译: 提供了在SiC衬底上方包括碳化硅(SiC)衬底和III族氮化物外延层的III族氮化物半导体器件结构。 III族氮化物外延层的位错密度小于约4×10 8 cm -2和/或至少约50V的隔离电压。

    Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices
    7.
    发明申请
    Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices 有权
    基于氮化物和碳化硅的集成器件以及制造基于氮化物的集成器件的方法

    公开(公告)号:US20060289901A1

    公开(公告)日:2006-12-28

    申请号:US11410768

    申请日:2006-04-25

    IPC分类号: H01L29/80 H01L21/338

    摘要: A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.

    摘要翻译: 单片电子器件包括包括多个氮化物外延层的第一氮化物外延结构。 多个氮化物外延层包括至少一个共同的氮化物外延层。 第二氮化物外延结构在第一氮化物外延结构的公共氮化物外延层上。 第一多个电触点在第一外延氮化物结构上,并且限定第一氮化物外延结构中的第一电子器件。 第二多个电触点位于第一外延氮化物结构上,并且在第二氮化物外延结构中限定第二电子器件。 单片电子器件包括具有注入的源极和漏极区域以及源极和漏极区域之间的注入沟道区域的半体绝缘碳化硅衬底和在碳化硅衬底的表面上的氮化物外延结构。 还公开了相应的方法。

    Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors

    公开(公告)号:US20060121682A1

    公开(公告)日:2006-06-08

    申请号:US11325735

    申请日:2006-01-05

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: H01L21/331

    CPC分类号: H01L29/7783 H01L29/2003

    摘要: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer. Nitride based heterojunction transistors having an AlGaN based bottom confinement layer, a GaN based channel layer on the bottom confinement layer and an AlGaN based barrier layer on the channel layer, the barrier layer having a higher concentration of aluminum than the bottom confinement layer, are also provided. Methods of fabricating such transistor are also provided.

    Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
    9.
    发明申请
    Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same 有权
    具有混合沟道层的半导体器件,电流孔径晶体管及其制造方法

    公开(公告)号:US20050258450A1

    公开(公告)日:2005-11-24

    申请号:US10849589

    申请日:2004-05-20

    申请人: Adam Saxler

    发明人: Adam Saxler

    摘要: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

    摘要翻译: 提供了包括源极接触,漏极接触和栅极接触的晶体管和/或制造晶体管的方法。 在一些实施例中,在源极和漏极接触之间提供沟道区,并且沟道区的至少一部分包括包含半导体材料的混合层。 在本发明的特定实施例中,晶体管是电流孔径晶体管。 沟道区可以包括侧向外延层或外延横向杂交层。 还提供了晶体管和制造电流孔径晶体管的方法,其包括延伸穿过沟道和阻挡层并且包括其中的半导体材料的沟槽。

    Current Aperture Transistors and Methods of Fabricating Same
    10.
    发明申请
    Current Aperture Transistors and Methods of Fabricating Same 有权
    电流孔径晶体管及其制造方法

    公开(公告)号:US20080029789A1

    公开(公告)日:2008-02-07

    申请号:US11871790

    申请日:2007-10-12

    申请人: Adam Saxler

    发明人: Adam Saxler

    IPC分类号: H01L29/768 H01L21/00

    摘要: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

    摘要翻译: 提供了包括源极接触,漏极接触和栅极接触的晶体管和/或制造晶体管的方法。 在一些实施例中,在源极和漏极接触之间提供沟道区,并且沟道区的至少一部分包括包含半导体材料的混合层。 在本发明的特定实施例中,晶体管是电流孔径晶体管。 沟道区可以包括侧向外延层或外延横向杂交层。 还提供了晶体管和制造电流孔径晶体管的方法,其包括延伸穿过沟道和阻挡层并且包括其中的半导体材料的沟槽。