公开(公告)号：US06643374B1

公开(公告)日：2003-11-04

申请号：US09283096

申请日：1999-03-31

申请人： Steven E. Wells ,  David A. Ward

发明人： Steven E. Wells ,  David A. Ward

IPC分类号： H04L926

CPC分类号： H04L9/0662 ,  H04L2209/12

摘要： A method and apparatus for producing a corrected bit stream from a random bit stream output by a random bit source. Sequential pairs of bits in the random bit stream are compared. If both bits in a pair of bits are identical, the output bits are discarded. If both bits in a pair of bits are different, one bit of the pair of bits is taken as the output bit.

摘要翻译： 一种用于由随机比特源输出的随机比特流产生校正比特流的方法和装置。 比较随机比特流中的比特序列。 如果一对位中的两个位相同，则输出位被丢弃。 如果一对比特中的两个比特不同，则将该比特中的一个比特作为输出比特。

公开(公告)号：US06687721B1

公开(公告)日：2004-02-03

申请号：US09541375

申请日：2000-03-31

申请人： Steven E. Wells ,  David A. Ward

发明人： Steven E. Wells ,  David A. Ward

IPC分类号： G06F102

CPC分类号： G06F7/588 ,  G06F7/582

摘要： A random number generator includes a random bit source to generate random bits and circuitry to process the generated random bits to accumulate entropy in the generated random bits. The random number generator also includes circuitry to output processed random bits selectively such that at least one processed random bit is not output.

摘要翻译： 随机数发生器包括随机位源以产生随机位和电路，以处理所生成的随机位以在生成的随机位中累积熵。 随机数生成器还包括有选择地输出处理的随机比特的电路，使得至少一个处理的随机比特不被输出。

公开(公告)号：US06728893B1

公开(公告)日：2004-04-27

申请号：US09553925

申请日：2000-04-21

申请人： Steven E. Wells ,  David A. Ward

发明人： Steven E. Wells ,  David A. Ward

IPC分类号： G06F132

CPC分类号： G06F7/588 ,  H04L9/0662 ,  H04L9/0861 ,  H04L2209/12

摘要： A system and method for controlling power are described. A computer system including a memory module and a random number generator is monitored. The random number generator is enabled to generate and process random bits. The memory module is enabled to receive and store the random bits generated. The memory module is then disabled.

摘要翻译： 描述用于控制功率的系统和方法。 监视包括存储器模块和随机数发生器的计算机系统。 随机数生成器被使能以产生和处理随机位。 存储器模块被使能以接收和存储生成的随机位。 然后内存模块被禁用。

公开(公告)号：US07177888B2

公开(公告)日：2007-02-13

申请号：US10633096

申请日：2003-08-01

申请人： Steven E. Wells

发明人： Steven E. Wells

IPC分类号： G06J1/00 ,  G06F1/02

CPC分类号： H03K3/84 ,  H03K3/017 ,  H03K5/1565

摘要： A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

摘要翻译： 从随机位源产生均匀占空比的方法。 该方法包括测试所述随机位源的占空比; 如果占空比基本上不是百分之五十，则改变电压源的输出电压; 并且迭代地改变电压源的输出电压，直到所述占空比大致为百分之五十。

公开(公告)号：US07085341B2

公开(公告)日：2006-08-01

申请号：US10614966

申请日：2003-07-08

申请人： Steven E. Wells

发明人： Steven E. Wells

IPC分类号： G06M3/00

CPC分类号： H03K21/403

摘要： A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

摘要翻译： 非易失性计数器。 非易失性存储器以不均匀基数的数字组织。 提供电路以增加响应于增量命令由数字表示的计数值。

公开(公告)号：US5835933A

公开(公告)日：1998-11-10

申请号：US19766

申请日：1993-02-19

申请人： Steven E. Wells ,  Virgil Niles Kynett ,  Terry L. Kendall ,  Richard Garner ,  Dave M. Brown

发明人： Steven E. Wells ,  Virgil Niles Kynett ,  Terry L. Kendall ,  Richard Garner ,  Dave M. Brown

IPC分类号： G06F3/06 ,  G06F9/445 ,  G06F12/02

CPC分类号： G06F3/0607 ,  G06F3/0632 ,  G06F3/0676 ,  G06F8/65

摘要： A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

公开(公告)号：US5581723A

公开(公告)日：1996-12-03

申请号：US20204

申请日：1993-02-19

申请人： Robert N. Hasbun ,  Steven E. Wells

发明人： Robert N. Hasbun ,  Steven E. Wells

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F12/0246 ,  G06F11/1435 ,  G06F2003/0694

摘要： A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase. With the enhanced process, a special identification is provided to the data regarding the management of the array stored on another block which is outside the normal identification range for the host computer so that the specially identified data is not lost during a power loss during an erase process and may be detected after power is restored to the system.

摘要翻译： 一种用于将快速EEPROM存储器阵列中的管理数据可靠地存储的方法，该阵列被划分为多个可单独擦除的存储器单元块，其中存储单元块中的每个块已经存储有关于在一个 清除过程，其中存储在第一块中的有效数据被写入阵列的另一个块，然后第一块被擦除。 该处理包括以下步骤：在第一块的擦除之前，将来自第一块的阵列的管理的数据存储在随机存取存储器中，并且在增强的处理中存储在另一个块上。 然后可以在擦除之后将数据重写到第一块。 通过增强处理，对存储在另一个块上的阵列的管理数据提供了特殊的标识，该数组在主计算机的正常识别范围之外，使得在擦除期间的功率损耗期间特殊识别的数据不会丢失 并且可以在电力恢复到系统之后被检测到。

公开(公告)号：US5574879A

公开(公告)日：1996-11-12

申请号：US541522

申请日：1995-10-10

申请人： Steven E. Wells ,  Kurt B. Robinson

发明人： Steven E. Wells ,  Kurt B. Robinson

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/56 ,  G11C2211/5641 ,  G11C8/00

摘要： A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory space and the physical addresses when operating in the standard cell mode.

摘要翻译： 存储器系统包含用于存储多个阈值电平的存储器单元，以表示“n”位数据的存储。 存储器系统包括用于生成多个物理地址的地址缓冲器，使得每个物理地址唯一地标识“j”个存储器单元的存储器位置。 为了寻址由单个物理地址标识的“n”位的一部分，地址缓冲器生成多级单元（MLC）地址。 存储器系统还包含用于允许选择多级单元（MLC）模式和标准单元模式的开关控制。 当存储器以标准单元模式运行时，选择电路允许每单元读取单个位，并且当存储器以多电平单元模式运行时，允许每个存储单元读取多个位数据。 本发明的寻址方案通过在以MLC模式操作时通过表现出存储器位置与物理地址之间的1对应关系来维持地址一致性，并且当在标准中操作时通过显示存储器空间和物理地址之间的1：1对应关系 单元格模式。

公开(公告)号：US5295113A

公开(公告)日：1994-03-15

申请号：US697716

申请日：1991-05-09

申请人： Patricia L. Dix ,  Steven E. Wells

发明人： Patricia L. Dix ,  Steven E. Wells

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/40

CPC分类号： G11C5/147 ,  G11C16/16 ,  G11C16/30

摘要： Circuitry for preventing slow erasing and slow programming in non-volatile semiconductor memories is disclosed. This circuitry establishes the potential on the source regions of cells in blocks not currently being programming so as to substantially prevent the occurrences of slow erasing and slow programming which can alter the state or condition of the cells.

摘要翻译： 公开了用于防止在非易失性半导体存储器中缓慢擦除和缓慢编程的电路。 该电路在当前未编程的块中确定单元的源区上的电位，以便基本上防止可能改变单元的状态或状态的缓慢擦除和缓慢编程的发生。

公开(公告)号：US5265059A

公开(公告)日：1993-11-23

申请号：US698547

申请日：1991-05-10

申请人： Steven E. Wells ,  Owen W. Jungroth ,  Mickey L. Fandrich

发明人： Steven E. Wells ,  Owen W. Jungroth ,  Mickey L. Fandrich

IPC分类号： G11C16/24 ,  G11C11/40

CPC分类号： G11C16/24

摘要： Circuitry for discharging a drain of a cell of a non-volatile semiconductor memory is described. A discharge transistor is coupled between (1) the drain of the cell and (2) ground for selectably (a) providing a discharge paths to ground for the drain of the cell when the discharge transistor is enabled and (b) not providing a discharge path to ground for the drain of the cell when the discharge transistor is not enabled. Circuitry is coupled to the discharge transistor for enabling the discharge transistor for a duration that both begins and ends (1) after a first operation is performed with respect to the cell and (2) before a verify operation is performed with respect to the cell.

摘要翻译： 描述了用于排放非易失性半导体存储器的单元的漏极的电路。 放电晶体管耦合在（1）电池的漏极和（2）接地之间，用于可选择地（a）当放电晶体管被使能时，为电池的漏极提供放电路径到地，并且（b）不提供放电 当放电晶体管未使能时，对于单元的漏极的接地路径。 电路耦合到放电晶体管，用于使得放电晶体管在相对于单元执行第一操作之后开始和结束（1）的持续时间，以及（2）在相对于单元执行验证操作之前。