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1.发明授权公开(公告)号：US06768338B1
公开(公告)日：2004-07-27
申请号：US10354587
申请日：2003-01-30
IPC分类号： G06F738
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译： 可用于例如实现可编程逻辑器件（PLD）的查找表的结构。 该结构包括配置存储单元，传输晶体管和缓冲器。 传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。 在第一工作电压下提供数据输入信号。 一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。 栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。
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2.发明授权Integrated circuit multiplexer including transistors of more than one oxide thickness 有权集成电路多路复用器包括多于一个氧化物厚度的晶体管公开(公告)号：US06949951B1
公开(公告)日：2005-09-27
申请号：US10869777
申请日：2004-06-15
IPC分类号： G06F7/38 , H03K17/00 , H03K17/693 , H03K19/177
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译： 可以用于例如可编程逻辑器件（PLD）中的多路复用器。 多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。 可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。 在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。 一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。
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3.发明授权公开(公告)号：US07053654B1
公开(公告)日：2006-05-30
申请号：US10869139
申请日：2004-06-15
IPC分类号： G06F7/38
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译： 可用于例如实现可编程逻辑器件（PLD）的查找表的结构。 该结构包括配置存储单元，传输晶体管和缓冲器。 传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。 在第一工作电压下提供数据输入信号。 一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。 栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。
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4.发明授权Integrated circuit multiplexer including transistors of more than one oxide thickness 有权集成电路多路复用器包括多于一个氧化物厚度的晶体管公开(公告)号：US06768335B1
公开(公告)日：2004-07-27
申请号：US10354520
申请日：2003-01-30
IPC分类号： G06F738
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译： 可以用于例如可编程逻辑器件（PLD）中的多路复用器。 多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。 可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。 在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。 一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。
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公开(公告)号：US07382157B1
公开(公告)日：2008-06-03
申请号：US11541986
申请日：2006-10-02
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/693 , H03K19/17728
摘要： Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.
摘要翻译： 互连驱动电路，可用于动态集成电路（IC）的互连结构，如动态可编程逻辑器件（PLD）。 示例性IC包括两个或多个逻辑电路和耦合在逻辑电路之间的两个或多个自复位互连驱动器电路。 每个自复位互连驱动器电路包括驱动缓冲电路的多路复用器电路。 在第一状态下，缓冲电路将第一值驱动到缓冲电路的输出端上。 在第二状态下，缓冲电路首先将第二值驱动到缓冲电路的输出端，然后返回到第一状态。 详细描述了几个不同的电路。
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6.发明授权Programmable lookup table with dual input and output terminals in shift register mode 有权可编程查找表，带有移位寄存器模式的双输入和输出端子公开(公告)号：US07215138B1
公开(公告)日：2007-05-08
申请号：US11152590
申请日：2005-06-14
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/17728 , H03K19/1776
摘要： A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N−1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N−2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.
摘要翻译： 用于集成电路（IC）的可编程查找表可选地在编程为用作移位寄存器逻辑时提供两个输入信号和两个输出信号到可编程IC的互连结构。 根据一个实施例，集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT），其中N是整数。 LUT可以被配置为用作具有输入信号移位和耦合到互连结构的一个输出信号的（2 **（N-1））位移位寄存器，或者作为二（2 **（N- 2）） - 具有耦合到互连结构的输入信号中的两个移位和两个输出信号的位移位寄存器。 在一些实施例中，移位寄存器的每个位包括LUT的两个存储单元，用作主锁存器的第一存储器单元和用作从锁存器的第二存储器单元。
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7.发明授权Six-input look-up table and associated memory control circuitry for use in a field programmable gate array 有权六输入查找表和用于现场可编程门阵列的相关存储器控制电路公开(公告)号：US07075332B1
公开(公告)日：2006-07-11
申请号：US10863989
申请日：2004-06-08
IPC分类号： G06F7/38 , H03K10/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder receives a first subset of the six input signals, and in response, provides a first set of write select signals to the 64 write control circuits. A second write address decoder receives a second subset of the six input signals and a write clock signal, and in response, provides a plurality of decoded write clock signals to the sixty-four write control circuits. A write data value, which is applied to each of the write control circuits, is written to one of the memory cells in a synchronous manner with respect to the write clock signal in response to the first set of write select signals and the decoded write clock signals.
摘要翻译： 6输入LUT架构包括64个存储器单元，其存储64个对应的数据值。 64个写控制电路耦合到64个存储单元。 第一写地址解码器接收六个输入信号的第一子集，并且作为响应，向64个写控制电路提供第一组写选择信号。 第二写地址解码器接收六个输入信号的第二子集和写时钟信号，并且作为响应，向64个写控制电路提供多个解码的写时钟信号。 响应于第一组写入选择信号和解码的写入时钟，写入数据值被施加到每个写入控制电路，以相对于写入时钟信号的同步方式被写入存储器单元之一 信号。
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公开(公告)号：US06294930B1
公开(公告)日：2001-09-25
申请号：US09479392
申请日：2000-01-06
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。
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公开(公告)号：US5877632A
公开(公告)日：1999-03-02
申请号：US837023
申请日：1997-04-11
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.
摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。
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10.发明授权Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure 有权可编程逻辑块，具有耦合到通用互连结构的专用和可选择的查找表输出公开(公告)号：US07375552B1
公开(公告)日：2008-05-20
申请号：US11151892
申请日：2005-06-14
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17736 , G06F7/5324 , G06F7/5443 , H03K19/17728
摘要： A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.
摘要翻译： 可编程逻辑块向集成电路（IC）中的通用互连结构提供两个查找表（LUT）输出信号，逻辑块的一个输出端专用于第一LUT输出信号，另一个输出端具有可选择的 可以将两个LUT输出信号中的任一个提供给通用互连结构的输入。 IC包括互连结构（例如，可编程互连结构）和耦合到互连结构的可编程逻辑块。 可编程逻辑块包括具有两个输出端的LUT。 第一LUT输出端子经由逻辑块的第一输出端子不可编程地耦合到互连结构。 第一和第二LUT输出端子都可以通过逻辑块的第二输出端子可编程地耦合到互连结构，例如经由可编程多路复用器在两个LUT输出端子之间进行选择。
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