Method to remove circuit patterns from a wafer
    1.
    发明授权
    Method to remove circuit patterns from a wafer 失效
    从晶片去除电路图案的方法

    公开(公告)号:US07666689B2

    公开(公告)日:2010-02-23

    申请号:US11609573

    申请日:2006-12-12

    IPC分类号: H01L21/00

    CPC分类号: B24C3/322

    摘要: A method holds wafers that contain patterned structures using a particle blasting tool. Next, the method directs particles at the patterned structures, such that the particles contact the patterned structures with a predetermined velocity and remove the patterned structures. This process of directing the particles at the wafer is controlled to stop directing the particles when substantially all of the patterned structures are removed from the wafer. This process also comprises selecting the particles to have a size equal to or less than 3 microns. For example, the particles can comprise aluminum oxide, silicon oxide, cerium, and/or a plastic. By maintaining the particle size equal to 3 microns or less, the blasting produces a substantially smooth wafer surface, thereby omitting the need for subsequent wafer polishing. Further, the wafers produced by such processing do not exhibit the highly stress lattice and fragile nature of wafers processed by wet processing.

    摘要翻译: 一种方法使用颗粒喷砂工具保持包含图案化结构的晶片。 接下来,该方法将颗粒引导到图案化结构,使得颗粒以预定速度接触图案化结构并去除图案化结构。 当基本上将所有图案化结构从晶片上移除时,控制在晶片处引导颗粒的这个过程以停止引导颗粒。 该方法还包括选择具有等于或小于3微米尺寸的颗粒。 例如,颗粒可以包括氧化铝,氧化硅,铈和/或塑料。 通过保持等于3微米或更小的粒度,喷砂产生基本上平滑的晶片表面,从而省去了随后的晶片抛光的需要。 此外,通过这种处理制造的晶片不会表现出通过湿法加工处理的晶片的高应力晶格和脆性。

    Method to Remove Circuit Patterns from a Wafer
    2.
    发明申请
    Method to Remove Circuit Patterns from a Wafer 失效
    从晶圆去除电路图案的方法

    公开(公告)号:US20080139088A1

    公开(公告)日:2008-06-12

    申请号:US11609573

    申请日:2006-12-12

    IPC分类号: B24B1/00

    CPC分类号: B24C3/322

    摘要: A method holds wafers that contain patterned structures using a particle blasting tool. Next, the method directs particles at the patterned structures, such that the particles contact the patterned structures with a predetermined velocity and remove the patterned structures. This process of directing the particles at the wafer is controlled to stop directing the particles when substantially all of the patterned structures are removed from the wafer. This process also comprises selecting the particles to have a size equal to or less than 3 microns. For example, the particles can comprise aluminum oxide, silicon oxide, cerium, and/or a plastic. By maintaining the particle size equal to 3 microns or less, the blasting produces a substantially smooth wafer surface, thereby omitting the need for subsequent wafer polishing. Further, the wafers produced by such processing do not exhibit the highly stress lattice and fragile nature of wafers processed by wet processing.

    摘要翻译: 一种方法使用颗粒喷砂工具保持包含图案化结构的晶片。 接下来,该方法将颗粒引导到图案化结构,使得颗粒以预定速度接触图案化结构并去除图案化结构。 当基本上将所有图案化结构从晶片上移除时,控制在晶片处引导颗粒的这个过程以停止引导颗粒。 该方法还包括选择具有等于或小于3微米尺寸的颗粒。 例如,颗粒可以包括氧化铝,氧化硅,铈和/或塑料。 通过保持等于3微米或更小的粒度,喷砂产生基本上平滑的晶片表面,从而省去了随后的晶片抛光的需要。 此外,通过这种处理制造的晶片不会表现出通过湿法加工处理的晶片的高应力晶格和脆性。

    METHOD TO RECOVER PATTERNED SEMICONDUCTOR WAFERS FOR REWORK
    3.
    发明申请
    METHOD TO RECOVER PATTERNED SEMICONDUCTOR WAFERS FOR REWORK 失效
    恢复图形化半导体晶体的方法

    公开(公告)号:US20080138989A1

    公开(公告)日:2008-06-12

    申请号:US12031726

    申请日:2008-02-15

    IPC分类号: H01L21/302

    CPC分类号: H01L21/02032

    摘要: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.

    摘要翻译: 公开了从半导体晶片的表面去除图案化电路结构的方法的实施例。 方法实施例包括用颗粒喷射半导体晶片的表面,以便基本上去除所有图案化的电路结构。 喷砂过程之后是一次或多次研磨,抛光和/或清洁工艺,以除去任何剩余的电路结构,去除任何晶格损伤和/或在半导体晶片的表面上实现期望的平滑度。

    Method to recover patterned semiconductor wafers for rework
    4.
    发明授权
    Method to recover patterned semiconductor wafers for rework 失效
    恢复图案化半导体晶片进行返工的方法

    公开(公告)号:US08034718B2

    公开(公告)日:2011-10-11

    申请号:US12031726

    申请日:2008-02-15

    IPC分类号: H01L21/302

    CPC分类号: H01L21/02032

    摘要: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.

    摘要翻译: 公开了从半导体晶片的表面去除图案化电路结构的方法的实施例。 方法实施例包括用颗粒喷射半导体晶片的表面,以便基本上除去所有图案化的电路结构。 喷砂过程之后是一次或多次研磨,抛光和/或清洁工艺,以除去任何剩余的电路结构,去除任何晶格损伤和/或在半导体晶片的表面上实现期望的平滑度。

    SILICON WAFER THINNING END POINT METHOD
    5.
    发明申请
    SILICON WAFER THINNING END POINT METHOD 有权
    硅氧化薄点法

    公开(公告)号:US20080124896A1

    公开(公告)日:2008-05-29

    申请号:US11563715

    申请日:2006-11-28

    IPC分类号: H01L21/461

    CPC分类号: H01L21/78

    摘要: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

    摘要翻译: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤:提供具有正面和背面的硅晶片,在晶片前侧构建集成电路,然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤:在晶片中形成期望的结构,并且在晶片中形成端部结构,所述端部结构延伸到比晶片的背面更大的深度,而不是期望的结构。 此外,除去步骤包括仅将该基材除去至端部结构的步骤,由此在除去步骤期间不除去所需结构的一部分。