公开(公告)号：US20060267090A1

公开(公告)日：2006-11-30

申请号：US11398467

申请日：2006-04-04

申请人： Steven Sapp ,  Hamza Yilmaz ,  Christopher Rexer ,  Daniel Calafut

发明人： Steven Sapp ,  Hamza Yilmaz ,  Christopher Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

摘要翻译： 单片集成场效应晶体管和肖特基二极管包括延伸到半导体区域的栅极沟槽。 源极区域具有位于栅极沟槽的每一侧的大致三角形形状。 接触开口延伸到相邻栅极沟槽之间的半导体区域中。 导体层填充接触开口以电接触：（a）源区域沿着每个源极区域的倾斜侧壁的至少一部分，以及（b）沿接触开口底部的半导体区域，其中导体 层与半导体区形成肖特基接触。

公开(公告)号：US07393749B2

公开(公告)日：2008-07-01

申请号：US11450903

申请日：2006-06-08

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

摘要翻译： 场效应晶体管如下形成。 提供了具有在半导体区域上延伸的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：US20080087963A1

公开(公告)日：2008-04-17

申请号：US11865191

申请日：2007-10-01

申请人： Daniel Calafut ,  Hamza Yilmaz ,  Steven Sapp

发明人： Daniel Calafut ,  Hamza Yilmaz ,  Steven Sapp

IPC分类号： H01L27/06

CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L29/7808 ,  H01L2924/0002 ,  H03K17/08122 ,  H03K17/0822 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

摘要翻译： 用于功率MOSFET的静电放电（ESD）保护网络包括并联支路，其包含多晶硅齐纳二极管和电阻器，用于保护栅极免受由ESD引起的高压引起的破坏。 分支可以具有相同或独立的路径，用于电压跨越栅极区域进入半导体衬底。 具体地，次级分支具有比主分支更高的击穿电压，使得电压在保护网络的两个分支上共享。 器件的ESD保护网络提供了更有效的设计，而不增加芯片上使用的空间。 ESD保护网络还可以与其他有源和无源器件如晶闸管，绝缘栅双极晶体管和双极结型晶体管一起使用。

公开(公告)号：US07767524B2

公开(公告)日：2010-08-03

申请号：US12582487

申请日：2009-10-20

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

摘要翻译： 形成电荷平衡MOSFET的方法包括以下步骤。 提供了具有第一导电类型的上覆外延层的衬底。 形成延伸穿过外延层并终止在衬底内的栅极沟槽。 形成栅极沟槽的侧壁和底表面的屏蔽电介质。 在栅极沟槽中形成屏蔽电极。 栅极电介质层沿栅极沟槽的上侧壁形成。 栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。 形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。 深凹坑填充有第二导电类型的硅材料。

公开(公告)号：US20120156845A1

公开(公告)日：2012-06-21

申请号：US13325047

申请日：2011-12-13

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches.

摘要翻译： 用于形成场效应晶体管和肖特基二极管的方法包括在要形成场效应晶体管的硅区域的第一部分中形成阱区，但在肖特基二极管的硅区域的第二部分中不形成阱区 形成。 形成延伸到硅区域的栅极沟槽。 在每个栅极沟槽中形成凹陷栅极。 在每个凹入的栅极上形成电介质盖。 井区域的露出表面是凹进的，以在每两个相邻沟槽之间形成一个凹槽。 在不掩蔽有效区域的任何部分的情况下，执行零度覆盖植入以在每两个相邻沟槽之间的阱区域中形成第二导电类型的重体区域。

公开(公告)号：US20090111227A1

公开(公告)日：2009-04-30

申请号：US12346626

申请日：2008-12-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions.

摘要翻译： 用于形成具有有源区和围绕有源区的端接区的场效应晶体管的方法包括在阱区和第一硅区具有相反导电类型的第一硅区中形成阱区。 形成延伸穿过阱区并终止在第一硅区内的栅极沟槽。 在每个栅极沟槽中形成凹陷栅极。 在每个凹入的栅极上形成电介质盖。 阱区域在相邻沟槽之间凹陷以暴露每个电介质盖的上侧壁。 进行覆盖源植入以在每两个相邻沟槽之间的凹陷区域的上部中形成第二硅区域。 沿着电介质盖的每个暴露的上侧壁形成介电间隔物，每两个相邻的电介质间隔物位于每两个相邻栅极沟槽之间，形成在第二硅区上的开口。 第二硅区域在每两个相邻的电介质间隔物之间​​通过开口凹进，使得只有介电间隔物正下方的第二硅区域的部分保留。 第二硅区域的剩余部分形成源区域。

公开(公告)号：US07514322B2

公开(公告)日：2009-04-07

申请号：US12125242

申请日：2008-05-22

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.

摘要翻译： FET包括半导体区域中的沟槽。 沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。 半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。 第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。 第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。 半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

公开(公告)号：US20080258213A1

公开(公告)日：2008-10-23

申请号：US12125242

申请日：2008-05-22

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.

摘要翻译： FET包括半导体区域中的沟槽。 沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。 半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。 第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。 第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。 半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

公开(公告)号：US20100258855A1

公开(公告)日：2010-10-14

申请号：US12822008

申请日：2010-06-23

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20100038708A1

公开(公告)日：2010-02-18

申请号：US12582487

申请日：2009-10-20

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

摘要翻译： 形成电荷平衡MOSFET的方法包括以下步骤。 提供了具有第一导电类型的上覆外延层的衬底。 形成延伸穿过外延层并终止在衬底内的栅极沟槽。 形成栅极沟槽的侧壁和底表面的屏蔽电介质。 在栅极沟槽中形成屏蔽电极。 栅极电介质层沿栅极沟槽的上侧壁形成。 栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。 形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。 深凹坑填充有第二导电类型的硅材料。