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    FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM
    1.
    发明申请
    FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM 有权
    具有指定读取SCRUB算法的闪存

    公开(公告)号：US20130346805A1

    公开(公告)日：2013-12-26

    申请号：US13529522

    申请日：2012-06-21

    申请人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

    发明人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

    IPC分类号： G06F11/28

    CPC分类号： G11C16/3418 ,  G11B20/18 ,  G11B20/1883 ,  G11C16/3427 ,  G11C16/3431

    摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

    摘要翻译： 已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。 该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。 控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。 然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。 块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

    Flash memory with targeted read scrub algorithm
    2.
    发明授权
    Flash memory with targeted read scrub algorithm 有权
    具有目标读取擦除算法的闪存

    公开(公告)号：US09053808B2

    公开(公告)日：2015-06-09

    申请号：US13529522

    申请日：2012-06-21

    申请人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

    发明人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

    IPC分类号： G06F11/00 ,  G11C16/34 ,  G11B20/18

    CPC分类号： G11C16/3418 ,  G11B20/18 ,  G11B20/1883 ,  G11C16/3427 ,  G11C16/3431

    摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

    摘要翻译： 已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。 该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。 控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。 然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。 块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

    Balanced Performance for On-Chip Folding of Non-Volatile Memories
    3.
    发明申请
    Balanced Performance for On-Chip Folding of Non-Volatile Memories 有权
    非易失性存储器片上折叠的平衡性能

    公开(公告)号：US20120311244A1

    公开(公告)日：2012-12-06

    申请号：US13491879

    申请日：2012-06-08

    申请人： Yichao Huang ,  Jianmin Huang ,  Gautam Ashok Dusija ,  Oleg Kragel

    发明人： Yichao Huang ,  Jianmin Huang ,  Gautam Ashok Dusija ,  Oleg Kragel

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1042 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    摘要： A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands.

    摘要翻译： 非易失性存储器系统接收并存储主机数据。 当存储器系统接收主机数据时，它首先以二进制格式写入数据，然后对数据执行片上折叠操作，以多状态格式存储数据。 存储器系统对折叠操作的相位进行交织，使得在分配单元之间使得性能更均匀，其中主机根据分配单元存储数据。 存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作，其中控制器还平衡操作，使得在相对于分配单元的平面之间的性能更均匀，因为从 主办。 为了进一步维持性能，内存系统使用一个空闲块列表，该列表具有一个只能用于一组指定命令的预留部分。

    OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY
    4.
    发明申请
    OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY 有权
    优化的非易失性存储器页面编程订单

    公开(公告)号：US20110010484A1

    公开(公告)日：2011-01-13

    申请号：US12499219

    申请日：2009-07-08

    申请人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

    发明人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G11C11/5628 ,  G11C2211/5648

    摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

    摘要翻译： 在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。 对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。 由于发生更大程度的并行处理，记录单元的整体编程时间减少。 当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。 编程完成后，存储器信号通知主机传送下一个记录单元。 数据页可以包括下页，中页和上页。

    Balanced performance for on-chip folding of non-volatile memories
    5.
    发明授权
    Balanced performance for on-chip folding of non-volatile memories 有权
    平衡性能，用于非易失性存储器的片上折叠

    公开(公告)号：US08725935B2

    公开(公告)日：2014-05-13

    申请号：US13491879

    申请日：2012-06-08

    申请人： Yichao Huang ,  Jianmin Huang ,  Gautam Ashok Dusija ,  Oleg Kragel

    发明人： Yichao Huang ,  Jianmin Huang ,  Gautam Ashok Dusija ,  Oleg Kragel

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1042 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    摘要： A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations. When the memory system needs a memory block for the writing of data, it selects blocks from a free block list, where the free block list includes a reserve portion that is only accessible for a specified set of commands.

    摘要翻译： 非易失性存储器系统接收并存储主机数据。 当存储器系统接收主机数据时，它首先以二进制格式写入数据，然后对数据执行片上折叠操作，以多状态格式存储数据。 存储器系统交织折叠操作的阶段，其中主机根据分配单元存储数据。 存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作，其中控制器还平衡操作。 当存储器系统需要用于写入数据的存储器块时，它从空闲块列表中选择块，其中空闲块列表包括仅可用于指定的一组命令的预留部分。

    Optimized page programming order for non-volatile memory
    6.
    发明授权
    Optimized page programming order for non-volatile memory 有权
    针对非易失性存储器优化页面编程顺序

    公开(公告)号：US08180994B2

    公开(公告)日：2012-05-15

    申请号：US12499219

    申请日：2009-07-08

    申请人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

    发明人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

    IPC分类号： G06F12/00

    CPC分类号： G11C11/5628 ,  G11C2211/5648

    摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

    摘要翻译： 在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。 对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。 由于发生更大程度的并行处理，记录单元的整体编程时间减少。 当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。 编程完成后，存储器信号通知主机传送下一个记录单元。 数据页可以包括下页，中页和上页。

    System and method for pre-interleaving sequential data
    7.
    发明授权
    System and method for pre-interleaving sequential data 有权
    用于预交错顺序数据的系统和方法

    公开(公告)号：US09329989B2

    公开(公告)日：2016-05-03

    申请号：US13341704

    申请日：2011-12-30

    申请人： Steven Sprouse ,  Yichao Huang

    发明人： Steven Sprouse ,  Yichao Huang

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/7208 ,  G11C7/1042

    摘要： A method and system for operating a memory device in programming mode is disclosed. The memory device includes a programming mode and a normal mode. The memory device in programming mode increases the number of physical planes that can be programmed in parallel than can be programmed in normal mode. In this way, the memory device may be programmed more quickly at various times of operation of the memory device (such as during manufacturing). The host system may send rearranged data to the memory device in programming mode with the rearranged data accounting for the increased number of physical planes programmed in parallel.

    摘要翻译： 公开了一种在编程模式下操作存储器件的方法和系统。 存储器件包括编程模式和正常模式。 编程模式下的存储器件可以增加可编程并行编程的物理平面数量，而不是在正常模式下编程。 以这种方式，可以在存储器件的各种操作时间（例如在制造期间），更快地编程存储器件。 主机系统可以在编程模式下将重新排列的数据发送到存储器件，重新排列的数据表示并行编程的物理平面数量的增加。

    System and Method for Pre-interleaving Sequential Data
    8.
    发明申请
    System and Method for Pre-interleaving Sequential Data 有权
    用于预交错顺序数据的系统和方法

    公开(公告)号：US20130173874A1

    公开(公告)日：2013-07-04

    申请号：US13341704

    申请日：2011-12-30

    申请人： Steven Sprouse ,  Yichao Huang

    发明人： Steven Sprouse ,  Yichao Huang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/7208 ,  G11C7/1042

    摘要： A method and system for operating a memory device in programming mode is disclosed. The memory device includes a programming mode and a normal mode. The memory device in programming mode increases the number of physical planes that can be programmed in parallel than can be programmed in normal mode. In this way, the memory device may be programmed more quickly at various times of operation of the memory device (such as during manufacturing). The host system may send rearranged data to the memory device in programming mode with the rearranged data accounting for the increased number of physical planes programmed in parallel.

    摘要翻译： 公开了一种在编程模式下操作存储器件的方法和系统。 存储器件包括编程模式和正常模式。 编程模式下的存储器件可以增加可编程并行编程的物理平面数量，而不是在正常模式下编程。 以这种方式，可以在存储器件的各种操作时间（例如在制造期间），更快地编程存储器件。 主机系统可以在编程模式下将重新排列的数据发送到存储器件，重新排列的数据表示并行编程的物理平面数量的增加。