公开(公告)号：US08527257B2

公开(公告)日：2013-09-03

申请号：US13175456

申请日：2011-07-01

申请人： Subodh M. Reddy ,  William Walker

发明人： Subodh M. Reddy ,  William Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

摘要翻译： 一种方法可以包括基于逻辑单元的数字模型的分析来生成用于逻辑单元的逻辑转换数据，逻辑转换数据包括指示响应于输入转换而发生的逻辑单元的输出转换的至少一个条目 的逻辑单元。 该方法还可以包括为逻辑单元生成参数化的基于过渡的模拟模型，参数化的基于过渡的模拟模型包括与逻辑转换数据的每个条目相关联的转换时序参数。 该方法还可以包括基于参数化的基于过渡的模拟模型和表征逻辑单元的一个或多个模拟网表来为逻辑单元生成模拟模型。

公开(公告)号：US20130006595A1

公开(公告)日：2013-01-03

申请号：US13175456

申请日：2011-07-01

申请人： Subodh M. Reddy ,  William Walker

发明人： Subodh M. Reddy ,  William Walker

IPC分类号： G06G7/62

CPC分类号： G06F17/5036

摘要： A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

摘要翻译： 一种方法可以包括基于逻辑单元的数字模型的分析来生成用于逻辑单元的逻辑转换数据，逻辑转换数据包括指示响应于输入转换而发生的逻辑单元的输出转换的至少一个条目 的逻辑单元。 该方法还可以包括为逻辑单元生成参数化的基于过渡的模拟模型，参数化的基于过渡的模拟模型包括与逻辑转换数据的每个条目相关联的转换时序参数。 该方法还可以包括基于参数化的基于过渡的模拟模型和表征逻辑单元的一个或多个模拟网表来为逻辑单元生成模拟模型。

公开(公告)号：US09280628B2

公开(公告)日：2016-03-08

申请号：US13214859

申请日：2011-08-22

申请人： William Walker ,  Subodh M. Reddy

发明人： William Walker ,  Subodh M. Reddy

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

摘要翻译： 根据本公开的一些实施例，用于构建时钟网络的方法包括接收时钟网络的设计规范。 该方法还包括基于设计规范来确定时钟网络的拓扑。 拓扑结构指示时钟网络的多个级别中的至少一个，每个级别的缓冲器类型和用于每个级别的缓冲器扇出。 该方法还包括基于确定的拓扑来确定时钟网络的设计参数，并且生成包括设计参数的时钟网络综合工具规范文件。 该方法还包括使用规范文件合成时钟网络，使得时钟网络包括所确定的拓扑，并且使得时钟网络将来自时钟发生器的时钟信号同时分配到时钟网络的端点。

公开(公告)号：US20130055186A1

公开(公告)日：2013-02-28

申请号：US13214859

申请日：2011-08-22

申请人： William Walker ,  Subodh M. Reddy

发明人： William Walker ,  Subodh M. Reddy

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

摘要翻译： 根据本公开的一些实施例，用于构建时钟网络的方法包括接收时钟网络的设计规范。 该方法还包括基于设计规范来确定时钟网络的拓扑。 拓扑结构指示时钟网络的多个级别中的至少一个，每个级别的缓冲器类型和用于每个级别的缓冲器扇出。 该方法还包括基于确定的拓扑来确定时钟网络的设计参数，并且生成包括设计参数的时钟网络综合工具规范文件。 该方法还包括使用规范文件合成时钟网络，使得时钟网络包括所确定的拓扑，并且使得时钟网络将来自时钟发生器的时钟信号同时分配到时钟网络的端点。

公开(公告)号：US09147002B2

公开(公告)日：2015-09-29

申请号：US13562876

申请日：2012-07-31

申请人： Subodh M. Reddy ,  Kanji Uchino

发明人： Subodh M. Reddy ,  Kanji Uchino

IPC分类号： G06F15/16 ,  G06F17/30 ,  G09B5/06 ,  G09B7/02 ,  G09B19/00

CPC分类号： G06F17/30873 ,  G09B5/06 ,  G09B7/02 ,  G09B19/0053

摘要： A method includes storing content graph information regarding individual items of content accessed by one or more users of a system, storing path graph information comprising the order in which each of the one or more users accessed individual items of content, and selecting individual items of content to be presented to a subsequent user of the system and an order in which such individual items of content are presented to the subsequent user based on the stored content graph information and the stored path graph information.

摘要翻译： 一种方法包括存储关于由系统的一个或多个用户访问的单个内容项目的内容图形信息，存储包括一个或多个用户中的每一个访问单独内容的顺序的路径图信息，并且选择单独的内容项目 被呈现给系统的后续用户，并且基于所存储的内容图形信息和存储的路径图信息，将这些单独的内容项目呈现给后续用户的顺序。

公开(公告)号：US08255196B2

公开(公告)日：2012-08-28

申请号：US12197572

申请日：2008-08-25

申请人： William W. Walker ,  Subodh M. Reddy ,  Ranjeez Murgai

发明人： William W. Walker ,  Subodh M. Reddy ,  Ranjeez Murgai

IPC分类号： G06F17/50

CPC分类号： G06F1/10 ,  G06F17/5036 ,  G06F2217/62

摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。

公开(公告)号：US07801718B2

公开(公告)日：2010-09-21

申请号：US11680020

申请日：2007-02-28

申请人： Subodh M. Reddy ,  Gustavo R. Wilke ,  Rajeev Murgai

发明人： Subodh M. Reddy ,  Gustavo R. Wilke ,  Rajeev Murgai

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit residing outside of the window is also created. Monte Carlo simulations are performed on the combination of the accurate model and the approximate model to determine a plurality of timing values, wherein each run of the Monte Carlo simulation varies one or more parameters potentially affecting the operation of the mesh circuit. An uncertainty associated with the circuit elements is determined, based at least in part on the plurality of timing values. One embodiment considers clock as the signal whose timing uncertainty can be determined. Other embodiments model and simulate the global drive circuit that drives the mesh circuit separately from the mesh circuit to take into account common path correlations in the drive circuit.

摘要翻译： 分析定时不确定性的方法涉及创建驻留在覆盖网状电路的子集的窗口内的网状电路的一个或多个电路元件的精确模型。 还创建了位于窗户外部的网状电路的一个或多个电路元件的近似模型。 对精确模型和近似模型的组合执行蒙特卡罗模拟，以确定多个时间值，其中蒙特卡洛模拟的每次运行改变潜在地影响网格电路的操作的一个或多个参数。 至少部分地基于多个定时值来确定与电路元件相关联的不确定性。 一个实施例将时钟视为可以确定其定时不确定性的信号。 其他实施例模拟和模拟驱动网格电路与网状电路分离的全局驱动电路，以考虑驱动电路中的公共路径相关性。

公开(公告)号：US07788613B2

公开(公告)日：2010-08-31

申请号：US11428995

申请日：2006-07-06

申请人： William W. Walker ,  Subodh M. Reddy ,  Rajeev Murgai

发明人： William W. Walker ,  Subodh M. Reddy ,  Rajeev Murgai

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each original window location, expanding the original window location in one or more directions to generate a larger window location and generating a mesh simulation model including a detailed model inside the larger window location and an approximate model outside the larger window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.

摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集合，确定覆盖时钟网格的多个原始窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个原始窗口位置，在一个或多个方向上扩展原始窗口位置以生成更大的窗口位置并生成包括较大窗口位置内的详细模型的网格模拟模型以及较大窗口外的近似模型 位置，模拟网格模拟模型，并基于网格模拟模型测量窗口位置中的顺序元素的时钟时序。 该方法还包括基于原始窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。

公开(公告)号：US08799841B2

公开(公告)日：2014-08-05

申请号：US13434598

申请日：2012-03-29

申请人： Subodh M. Reddy ,  Toshiyuki Shibuya

发明人： Subodh M. Reddy ,  Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/08

摘要： According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components.

摘要翻译： 根据实施例的一个方面，设计模拟电路的方法可以包括为电路选择多个模拟分量。 该方法还可以包括对模拟组件进行排序。 该方法还可以包括为每个模拟分量的参数确定至少一个帕累托最优设计点。 每个模拟组件的帕累托最优设计点可以基于性能度量，相应模拟组件的参数以及由模拟量排序中的相应模拟组件之前的模拟组件的帕累托最优设计点产生的约束 组件。

公开(公告)号：US07802215B2

公开(公告)日：2010-09-21

申请号：US11754586

申请日：2007-05-29

申请人： Subodh M. Reddy ,  Rajeev Murgai

发明人： Subodh M. Reddy ,  Rajeev Murgai

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F1/10 ,  G06F2217/62

摘要： A method is provided and includes accessing a description of a chip, which includes sequential elements and a clock mesh. Items used include: the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh. Additionally, the method includes determining a plurality of original window locations covering the clock mesh. Further, for each original window location, the method includes expanding the original window location in one or more directions to generate a larger window location; generating a mesh simulation model inside the larger window location; simulating the mesh simulation model; measuring clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.

摘要翻译： 提供了一种方法，包括访问包括顺序元素和时钟网格的芯片的描述。 使用的项目包括：芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集。 另外，该方法包括确定覆盖时钟网格的多个原始窗口位置。 此外，对于每个原始窗口位置，该方法包括在一个或多个方向上扩展原始窗口位置以生成较大的窗口位置; 在较大的窗口位置内生成网格模拟模型; 模拟网格模拟模型; 基于网格仿真模型的模拟测量原始窗口位置中的顺序元素的时钟定时; 并且基于原始窗口位置中的顺序元素的测量时钟定时来收集芯片上所有顺序元件的定时信息。