公开(公告)号：US08527257B2

公开(公告)日：2013-09-03

申请号：US13175456

申请日：2011-07-01

申请人： Subodh M. Reddy ,  William Walker

发明人： Subodh M. Reddy ,  William Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

摘要翻译： 一种方法可以包括基于逻辑单元的数字模型的分析来生成用于逻辑单元的逻辑转换数据，逻辑转换数据包括指示响应于输入转换而发生的逻辑单元的输出转换的至少一个条目 的逻辑单元。 该方法还可以包括为逻辑单元生成参数化的基于过渡的模拟模型，参数化的基于过渡的模拟模型包括与逻辑转换数据的每个条目相关联的转换时序参数。 该方法还可以包括基于参数化的基于过渡的模拟模型和表征逻辑单元的一个或多个模拟网表来为逻辑单元生成模拟模型。

公开(公告)号：US09280628B2

公开(公告)日：2016-03-08

申请号：US13214859

申请日：2011-08-22

申请人： William Walker ,  Subodh M. Reddy

发明人： William Walker ,  Subodh M. Reddy

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

摘要翻译： 根据本公开的一些实施例，用于构建时钟网络的方法包括接收时钟网络的设计规范。 该方法还包括基于设计规范来确定时钟网络的拓扑。 拓扑结构指示时钟网络的多个级别中的至少一个，每个级别的缓冲器类型和用于每个级别的缓冲器扇出。 该方法还包括基于确定的拓扑来确定时钟网络的设计参数，并且生成包括设计参数的时钟网络综合工具规范文件。 该方法还包括使用规范文件合成时钟网络，使得时钟网络包括所确定的拓扑，并且使得时钟网络将来自时钟发生器的时钟信号同时分配到时钟网络的端点。

公开(公告)号：US20130006595A1

公开(公告)日：2013-01-03

申请号：US13175456

申请日：2011-07-01

申请人： Subodh M. Reddy ,  William Walker

发明人： Subodh M. Reddy ,  William Walker

IPC分类号： G06G7/62

CPC分类号： G06F17/5036

摘要： A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

摘要翻译： 一种方法可以包括基于逻辑单元的数字模型的分析来生成用于逻辑单元的逻辑转换数据，逻辑转换数据包括指示响应于输入转换而发生的逻辑单元的输出转换的至少一个条目 的逻辑单元。 该方法还可以包括为逻辑单元生成参数化的基于过渡的模拟模型，参数化的基于过渡的模拟模型包括与逻辑转换数据的每个条目相关联的转换时序参数。 该方法还可以包括基于参数化的基于过渡的模拟模型和表征逻辑单元的一个或多个模拟网表来为逻辑单元生成模拟模型。

公开(公告)号：US20130055186A1

公开(公告)日：2013-02-28

申请号：US13214859

申请日：2011-08-22

申请人： William Walker ,  Subodh M. Reddy

发明人： William Walker ,  Subodh M. Reddy

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

摘要翻译： 根据本公开的一些实施例，用于构建时钟网络的方法包括接收时钟网络的设计规范。 该方法还包括基于设计规范来确定时钟网络的拓扑。 拓扑结构指示时钟网络的多个级别中的至少一个，每个级别的缓冲器类型和用于每个级别的缓冲器扇出。 该方法还包括基于确定的拓扑来确定时钟网络的设计参数，并且生成包括设计参数的时钟网络综合工具规范文件。 该方法还包括使用规范文件合成时钟网络，使得时钟网络包括所确定的拓扑，并且使得时钟网络将来自时钟发生器的时钟信号同时分配到时钟网络的端点。

公开(公告)号：US08666105B2

公开(公告)日：2014-03-04

申请号：US12905380

申请日：2010-10-15

申请人： William Walker ,  Chris Matthews

发明人： William Walker ,  Chris Matthews

IPC分类号： H04R25/00

CPC分类号： B60R11/0217 ,  B60R2011/0036 ,  B60R2011/0052 ,  H04R1/026

摘要： Disclosed herein are embodiments of a speaker mounting assembly. In one such embodiment, the speaker mounting assembly comprises a speaker housing having a housing support surface, a speaker mounting bracket having a base surface, a projection extending from one of the speaker housing and the speaker mounting bracket and a mounting structure formed on the other of the speaker housing and the speaker mounting bracket. The mounting structure is configured to receive the projection such that the housing support surface contacts the base surface when the projection is received in the mounting structure. The mounting structure has an anti-rotation structure configured to prevent rotation of the speaker housing with respect to the speaker mounting bracket.

摘要翻译： 这里公开了扬声器安装组件的实施例。 在一个这样的实施例中，扬声器安装组件包括具有壳体支撑表面的扬声器壳体，具有基座表面的扬声器安装支架，从扬声器壳体和扬声器安装支架中的一个延伸的突出部和在另一个上形成的安装结构 的扬声器外壳和扬声器安装支架。 安装结构构造成接收突起，使得当突起被接收在安装结构中时，壳体支撑表面接触基座表面。 安装结构具有防旋转结构，其构造成防止扬声器壳体相对于扬声器安装支架旋转。

公开(公告)号：US20100312106A9

公开(公告)日：2010-12-09

申请号：US11160915

申请日：2005-07-14

申请人： Travis Blalock ,  William Walker ,  John Hossack

发明人： Travis Blalock ,  William Walker ,  John Hossack

IPC分类号： A61B8/00

CPC分类号： A61B8/4494 ,  A61B8/00 ,  A61B8/145 ,  A61B8/4483 ,  A61B8/4488 ,  A61B8/461 ,  A61B8/5207 ,  G01S7/52028 ,  G01S7/52034 ,  G01S7/5208 ,  G01S7/52085 ,  G01S15/8915 ,  G01S15/8959 ,  G01S15/8995 ,  G10K11/346

摘要： In some illustrative embodiments, an incoming signal from a transducer in an ultrasound imaging beam-former apparatus is applied to an in-phase sample-and-hold and a quadrature sample-and-hold. The quadrature sample-and-hold may be clocked a quarter period behind the in-phase sample-and-hold. The output of the sample-and-holds are applied to in-phase and quadrature analog-to-digital converters. A magnitude calculator receives the in-phase and quadrature digital values, and outputs a magnitude. A phase calculator receives the in-phase and quadrature digital values, and outputs a phase. An apodizer applies a difference between an amplitude of the outgoing signal and the magnitude and applies a first illumination to a image point in substantial proportion to the difference, and a phase rotator applies a second illumination to the image point in substantial proportion to the phase.

摘要翻译： 在一些说明性实施例中，来自超声波成像束形成装置中的换能器的输入信号被施加到同相采样保持和正交采样保持。 正交采样和保持可以在同相采样保持后四分之一时间钟。 采样和保持的输出应用于同相和正交模数转换器。 幅度计算器接收同相和正交数字值，并输出幅度。 相位计算器接收同相和正交数字值，并输出相位。 变迹器应用输出信号的振幅和幅度之间的差异，并且以与该差异相当大比例的方式对图像点施加第一照明，并且相位旋转器以与该相位相当比例的图像点施加第二照明。

公开(公告)号：US20070103199A1

公开(公告)日：2007-05-10

申请号：US11265550

申请日：2005-11-01

申请人： Nestor Tzartzanis ,  William Walker

发明人： Nestor Tzartzanis ,  William Walker

IPC分类号： H03K19/0175

CPC分类号： H04L25/0282 ,  H03K3/356191 ,  H03K3/35625 ,  H04L25/0272 ,  H04L25/0294 ,  Y10T83/2037 ,  Y10T83/204

摘要： Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.

摘要翻译： 本发明公开了采用差分电流模式感测的片上全球电信令系统和方法，与传统的逆变器中继器相比具有降低的延迟和能量消耗。 本发明可以用于点到点连接以及N到1连接。

公开(公告)号：US20070054697A1

公开(公告)日：2007-03-08

申请号：US11383792

申请日：2006-05-17

申请人： James Money ,  William Walker

发明人： James Money ,  William Walker

IPC分类号： H04B1/38 ,  H04M1/00

CPC分类号： H04B1/3822 ,  G06F1/1628 ,  G06F1/1698 ,  G06F1/266 ,  H04B1/3827 ,  H04L63/30 ,  H04W12/02 ,  H04W12/06 ,  H04W84/12 ,  H04W84/18

摘要： A system and kit for establishing voice, video and data communication between network communication devices of a wireless local area network are provided. The network communication devices each have a wireless access control unit operable at a computer-based device. The wireless access control unit is adapted to provide wireless network connectivity for the network communication device. An antenna is coupled with the wireless access control unit of the network communication device. A communication application is operable at the computer-based device to provide the network communication device with voice, video and data communication capabilities between the network communication devices forming the wireless local area network.

摘要翻译： 提供了一种用于在无线局域网的网络通信设备之间建立语音，视频和数据通信的系统和工具包。 网络通信设备各自具有在基于计算机的设备可操作的无线接入控制单元。 无线接入控制单元适于为网络通信设备提供无线网络连接。 天线与网络通信设备的无线接入控制单元耦合。 通信应用可在基于计算机的设备上操作以向网络通信设备提供形成无线局域网的网络通信设备之间的语音，视频和数据通信能力。

公开(公告)号：US20060261855A1

公开(公告)日：2006-11-23

申请号：US11433158

申请日：2006-05-12

申请人： Daniel Hillman ,  William Walker

发明人： Daniel Hillman ,  William Walker

IPC分类号： H03K19/00 ,  H01L25/00 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F1/3203 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/66 ,  H01L27/11807 ,  H03K19/0013 ,  Y02D10/171 ,  Y02D50/20

摘要： An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

公开(公告)号：US20050016918A1

公开(公告)日：2005-01-27

申请号：US10494029

申请日：2001-11-09

申请人： William Walker

发明人： William Walker

IPC分类号： B01D21/00 ,  B01D17/00

CPC分类号： B01D21/10 ,  B01D21/0006 ,  B01D21/2411 ,  B01D21/2416 ,  B01D21/2427 ,  B01D21/2444 ,  B01D21/245 ,  B01D21/26

摘要： A treatment vessel for separating contaminants from a base liquid is provided. The vessel comprises a first cylindrical portion, a frusto-conical portion, a second cylindrical portion and a conical portion, the conical portion having a bottom outlet arranged to discharge heavy contaminants from the vessel. Over time, the heavy contaminants settle on the sides of the conical and frusto-conical portions. In order to remove the settled contaminants, the vessel is provided with at least one clarified liquid inlet disposed at or proximate to the frusto-conical portion. The clarified liquid is sourced from either the treatment vessel itself, or another treatment vessel in the same system. The clarified liquid is reintroduced into the vessel in a manner so as to cause a downward circular flow to scour out the frusto-conical portion and the conical portion so as to assist in removal of heavy contaminants that settle on the sides thereof.

摘要翻译： 提供了用于从基础液体分离污染物的处理容器。 容器包括第一圆柱形部分，截头圆锥形部分，第二圆柱形部分和锥形部分，锥形部分具有设置成从容器排出重污染物的底部出口。 随着时间的推移，重的污染物沉淀在锥形和截头圆锥形部分的两侧。 为了除去沉降的污染物，容器设置有至少一个设置在截头圆锥形部分处或附近的澄清液体入口。 澄清液体来自于处理容器本身，或来自同一系统中的另一处理容器。 澄清的液体以这样的方式重新引入容器中，以便使向下的圆形流动冲出截头圆锥形部分和锥形部分，以帮助去除沉积在其侧面上的重污染物。